Create an LVDS TX Interface with PHY Clock

About this task

The following figure shows a completed LVDS TX interface, where n is the serialization width and m is the number of TX lanes.

Figure 1. Complete LVDS TX Interface Block Diagram
Note: Use LVDS TX blocks from the same side of the FPGA to minimize skew between data lanes and TX reference clock output in an LVDS TX interface.

Follow these steps to build an LVDS TX interface using the Efinity® Interface Designer.

Procedure

  1. Add a PLL block with the following settings:
    OptionDescription
    Resource You can use any PLL resource.
    Reference Clock Mode External
    Reference Clock Frequency Any
    Output Clock For LVDS serializer widths 2 - 10, define the output clocks so that you have one for the fast clock (serial) and one for the slow clock (parallel).
    Set the relationship between the clocks as
    Half rate:
    serial clock frequency = parallel clock frequency * (serialization / 2)
    Full rate:
    serial clock frequency = parallel clock frequency * serialization
    The serial clock phase shift should be between 45 and 135 degrees.
  2. Add a GPIO block with these settings to provide the reference clock input to the PLL:
    OptionDescription
    Mode Input
    Pin Name Any
    Connection Type pll_clkin
    GPIO Resource Assign the dedicated PLL_CLKIN pin that corresponds to the PLL you chose.
  3. Add an LVDS TX block with these settings:
    OptionDescription
    LVDS Type Transmitter (TX)
    LVDS Resource Any channel
    Mode Serial data output
    Enable Serialization On
    Half Rate If using half-rate serialization, turn on Enable Half-Rate Serialization.
    Serialization Width n
    Output Pin/Bus Name Any
    Serial Clock Pin Name Use the fast clock output name that corresponds to the PLL you chose.
    Parallel Clock Pin Name Use the slow clock output name that corresponds to the PLL you chose.
  4. Repeat step 3 for each LVDS TX data lane you want to implement.
  5. Add another LVDS block that will serve as the LVDS TX reference clock output:
    OptionDescription
    LVDS type Transmitter (TX)
    LVDS resource Any channel
    Mode Reference clock output
    Enable Serialization On
    Half Rate This setting should match what you used in step 3.
    Serialization width n
    Output pin/bus name Any
    Serial clock pin name Specify the fast clock output name that corresponds to the PLL you chose.
    Parallel clock pin name Use the slow clock output name that corresponds to the PLL you chose.