Titanium I/O Banks

Efinix FPGAs have input/output (I/O) banks for general-purpose usage. Each I/O bank has independent power pins. The number and voltages supported vary by FPGA and package.

Some I/O banks are merged at the package level by sharing VCCIO pins, these are called merged banks. Merged banks have underscores (_) between banks in the VCCIO name (e.g., 1B_1C means VCCIO for bank 1B and 1C are connected). Some of the banks in a merged bank may not have available user I/Os in the package. The following table lists banks that have available user I/Os in a package.

Table 1. Titanium I/O Banks by Package for Ti35 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
F100 1A, 2A 1.2, 1.35, 1.5, 1.8 – All 1A_4B, 2A_2B
1B, 3A, 3B 1.2, 1.35, 1.5, 1.8 – All 3B_4A
BL 1.8, 2.5, 3.0, 3.3 All –
F100S3F2 1A, 2A 1.2, 1.35, 1.5, 1.81 – All 1A_4B, 2A_2B
1B, 3A, 3B 1.2, 1.35, 1.5, 1.8 – All 3B_4A
BL 1.8, 2.5, 3.0, 3.3 All –
F225
F256
 BL, TL, TR, BR, 1.8, 2.5, 3.0, 3.3 All –
1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
Table 2. Titanium I/O Banks by Package for Ti60 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
W64, V64 1A, 1B, 3B 1.2, 1.35, 1.5, 1.8 – All 1A_4B, 1B_2A, 2B_3A_3B_4A
F100 1A, 2A 1.2, 1.35, 1.5, 1.8 – All 1A_4B, 2A_2B
1B, 3A, 3B 1.2, 1.35, 1.5, 1.8 – All 3B_4A
BL 1.8, 2.5, 3.0, 3.3 All –
F100S3F2 1A, 2A 1.2, 1.35, 1.5, 1.82 – All 1A_4B, 2A_2B
1B, 3A, 3B 1.2, 1.35, 1.5, 1.8 – All 3B_4A
BL 1.8, 2.5, 3.0, 3.3 All –
F225
F256
 BL, TL, TR, BR, 1.8, 2.5, 3.0, 3.3 All –
1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
Table 3. Titanium I/O Banks by Package for Ti80 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
F225 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL, BR, TL, TR 1.8, 2.5, 3.0, 3.3 All –
Table 4. Titanium I/O Banks by Package for Ti90 and Ti120 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
J361 2B, 2C, 3A, 3B, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All 2A_2B, 3B_3C
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All –
J484 2B, 3A, 3B, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All 2A_2B_2C, 3B_3C
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All –
L484 2B, 3A, 3B, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All 2A_2B_2C, 3B_3C
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 – All –
G400, G529 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All –
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All –
Table 5. Titanium I/O Banks by Package for Ti85 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
N441 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL2, BR0, BR1, TL3, TR1 1.8, 2.5, 3.0, 3.3 All –
N484 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL3, TR1, BR0, BR1 1.8, 2.5, 3.0, 3.3 All BR1_BL3
N576 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL2, BL3, BR0, BR1, TL3, TR1 1.8, 2.5, 3.0, 3.3 All –
N676 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL0, BL1, BL2, BL3, BR0, BR1, TL2, TL3, TR1, TR2, TR3, TR5 1.8, 2.5, 3.0, 3.3 All –
Table 6. Titanium I/O Banks by Package for Ti125 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
F225 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL, BR, TL, TR 1.8, 2.5, 3.0, 3.3 All –
Table 7. Titanium I/O Banks by Package for Ti135 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
N441 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL2, BR0, BR1, TL3, TR1 1.8, 2.5, 3.0, 3.3 All –
N484 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL3, TR1, BR0, BR1 1.8, 2.5, 3.0, 3.3 All BR1_BL3
N576 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL2, BL3, BR0, BR1, TL3, TR1 1.8, 2.5, 3.0, 3.3 All –
N576D2F4 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.83 – All –
BL1, BL2, BL3, BR0, BR1, TL2, TL3, TR1 1.8, 2.5, 3.0, 3.3 All –
N676 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 – All –
BL0, BL1, BL2, BL3, BR0, BR1, TL2, TL3, TR1, TR2, TR3, TR5 1.8, 2.5, 3.0, 3.3 All –
Table 8. Titanium I/O Banks by Package for Ti180 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
J361 2B, 2C, 3A, 3B, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All 2A_2B, 3B_3C
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All –
J484, M484 2B, 3A, 3B, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All 2A_2B_2C, 3B_3C
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All –
J484D1 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All 2A_2B
BL, TL, TR, BR 1.8. 2.5, 3.0, 3.3 All –
L484 2B, 3A, 3B, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All 2A_2B_2C, 3B_3C
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All –
G400, G529 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 – All –
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All –
Table 9. Titanium I/O Banks by Package for Ti165, Ti240, and Ti375 FPGAs
Package GPIO Type I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
N484 HSIO 2B, 2C, 2D, 2E, 4B, 4C, 4D 1.2, 1.35, 1.5, 1.8 – All 2A_2B_2C, 4A_4B
HVIO BR0, BR3, TR1 1.8. 2.5, 3.0, 3.3 Yes All BR3_BR4
C529 HSIO 2A, 2B, 2C, 2D, 2E, 4B, 4C, 4D 1.2, 1.35, 1.5, 1.8 – All 4A_4B
HVIO BL2, BL3, BR0, BR3, TL1, TL5, TR0, TR1, TR2 1.8. 2.5, 3.0, 3.3 Yes All BR3_BR4,
TL1_TL5
BL2_BL3
N900 HSIO 2A, 2B, 2C, 2D, 2E, 4A, 4B, 4C, 4D 1.2, 1.35, 1.5, 1.8 – All –
HVIO BL2, BL3, BR0, BR3, BR4, TL0, TL1, TL5, TR1 1.8. 2.5, 3.0, 3.3 Yes All TL1_TL5
N1156 HSIO 2A, 2B, 2C, 2D, 2E, 4A, 4B, 4C, 4D 1.2, 1.35, 1.5, 1.8 – All –
HVIO BL0, BL1, BL2, BL3, BR0, BR1, BR3, BR4, TL0, TL1, TL5, TR0, TR1, TR2, TR3, TR5 1.8. 2.5, 3.0, 3.3 Yes All TL1_TL5
Notice: Refer to the FPGA pinout for information on the I/O bank assignments.
1 The SPI flash memory's VCC is connected to VCCIO1A_4B. If you are using the SPI flash memory, drive the VCCIO1A_4B with a 1.8 V supply.
2 The SPI flash memory's VCC is connected to VCCIO1A_4B. If you are using the SPI flash memory, drive the VCCIO1A_4B with a 1.8 V supply.
3 The SPI flash memory's VCC is connected to VCCIO4A. If you are using the SPI flash memory, drive VCCIO4A with a 1.8 V supply.