Design Check: LVDS Messages

When you check your design, the Interface Designer applies design rules to your LVDS settings. The following tables show some of the error and warning messages you may encounter and explains how to fix them.

lvds_rule_bidir_tx (error)

Message Output enable pin name must be configured in Bidirectional LVDS Tx
To fix If you are using a bidirectional LVDS block, you need to specify the output enable pin name.

lvds_rule_clkout_mode (error)

Message Serial clock name must be configured in clock output mode
To fix When you are using the LVDS serializer (serialization width greater than 1), you need to specify the serial clock pin name.
Message Parallel clock name must be configured in clock output mode
To fix When you are using the LVDS serializer (serialization width greater than 1), you need to specify the parallel clock pin name.
Message Clock output mode is not supported with serialization width 1
To fix When you set the serialization width to 1, you are bypassing the serializer and using the block as a simple buffer. As a simple buffer, you cannot use the block as a reference clock output. Change the serialization width.
Message Clock output mode is not supported with serialization disabled
To fix If you turn off Enable Serialization, you are bypassing the serializer and using the block as a simple buffer. As a simple buffer, you cannot use the block as a reference clock output. Turn on Enable Serialization and set the serialization width.

lvds_rule_deserial_rate (error)

Message Half rate deserialization only allowed with even deserialization width
To fix When you turn on Enable Half Rate Serialization, you can only use an even number for the deserialization width. Change the width to an even number or turn the option off.

lvds_rule_output_mode (error)

Message Instance of LVDS Tx has invalid configuration
To fix The block settings are not correct. It might be best to remove the block and start over :)
Message Output name must be configured in data output mode
To fix Specify a valid pin name.
Message Parallel clock name must be configured in data output mode
To fix When you are using the LVDS serializer (serialization width greater than 1), you need to specify the parallel clock pin name.
Message Serial clock name must be configured in data output mode
To fix When you are using the LVDS serializer (serialization width greater than 1), you need to specify the serial clock pin name.

lvds_rule_resource (error)

Message Resource name is empty
Resource <string> is not a valid LVDS device instance
To fix You need to choose a valid resource.

lvds_rule_resource_excluded (error)

Message Resource <resource> is excluded in Package Planner. Please use another resource
To fix The pins for the affected resource have been excluded in the Package Planner, and cannot be assigned. Remove the excluded setting in the Package Planner or choose another resource.

lvds_rule_usage (error)

Message Resource <res name> was assigned multiple times
To fix You cannot assign the same resource to more than one block type. Change the resource to a different one.

lvds_rule_rx_alt_conn (error)

Message Connection type <type> is not supported by the resource
To fix If you want to use the alternate funciton of an LVDS block, you need to choose a resource that supports it. You can filter for resources by alternate function in the Resource Assigner.
Message The resource only supports normal connection type
To fix You need to choose the normal connection type or assign a different resource that supports the connection type you want to use. You can filter for resources by alternate function in the Resource Assigner.

lvds_rule_alt_conn (warning)

Message Connection type <type> must be used by valid PLL
To fix The LVDS block is connected to a PLL clock input but is the resource you assigned does not support the pll_clkin alternate function. Choose a different resource that supports it. You can filter resources by alternate function in the Resource Assigner.
Message Connection type <type> cannot be used on an unbonded resource
To fix You get this error if the resource you choose is not available in the FPGA/package combination you are using. Choose another resource.
Message pll_clkin connection to PLL clock source not being used in <instance>
To fix The LVDS block is set to be a PLL reference clock (pll_clkin connection type) but the PLL is not configured to use it. Make sure that the clock you are choosing in the PLL is associated with this GPIO's resource.
Message pll_clkin connection to PLL clock source but none of the external clock source in PLL <instance> is selected
To fix The LVDS block is set to be a PLL reference clock (pll_clkin connection type) but the PLL is not configured to use it. In the PLL block, choose external or dynamic as the Clock Source and make sure that the clock you are choosing is associated with this GPIO's resource.
Message pll_clkin connection to PLL clock source but PLL Clock source on <instance> is set to core
To fix The LVDS block is set to be a PLL reference clock (pll_clkin connection type) but the PLL is not configured to use it. In the PLL block, choose external or dynamic as the Clock Source and make sure that the clock you are choosing is associated with this GPIO's resource.
Message pll_extfb connection to PLL external feedback pin but PLL feedback on <inst> is not set to default
To fix The LVDS block is set to be external feedback for the PLL (pll_extfb connection type) but the PLL is not configured to use it. In the PLL Clock Calculator, choose External as the Feedback Mode.

lvds_rule_rx_clock (error)

Message Serial and parallel clocks cannot be the same clock
To fix You cannot use the same clock for both the serial (FASTCLK) and parallel (SLOWCLK) clocks.
Message Serial clock name is not a PLL output clock
To fix Use a PLL output clock as the serial (FASTCLK) clock.
Message Parallel clock name is not a PLL output clock
To fix Use a PLL output as the parallel (SLOWCLK) clock.
Message Serial and parallel clocks are not from the same PLL instance
To fix You need to use the same PLL to generate both clocks.
Message Invalid phase shift difference: <phase shift difference> = Serial: <serial clk shifted time> - Parallel: <parallel clk shifted time> (max=<max shift difference allowed>, min=<min shift difference allowed>)
To fix Adjust the phase shift for the serial clock and parallel clock to ensure that the phase-shifted time difference falls within the range of 45 to 135 degrees, relative to the phase-shifted time of the serial clock.
Message Serial clock frequency has to be <float> times faster than parallel clock
To fix Make sure that the PLL output clock frequencies are set correctly.
Half rate calculation—serial clock frequency = parallel clock frequency * (serialization / 2)
Full rate calculation—serial clock frequency = parallel clock * serialization
Message Invalid phase shift difference: {phase shift difference} = Serial: {serial clk shifted time} - Parallel: {parallel clk shifted time} (max={max shift difference allowed}, min={min shift difference allowed)
Example: Invalid phase shift difference: 0.0000 ps = Serial: 400.0000 ps = Parallel: 400.0000 ps (max=600.0000 ps, min = 200.0000 ps)
To fix

Adjust the phase shift for the serial clock and parallel clock to ensure that the phase-shifted time difference falls within the specified range.

lvds_rule_rx_clock_region (error)

Message Serial and Parallel clocks generated by PLL have to be driven to the same clock network. <Serial|Parallel> clock <name> was generated by PLL output clock 4 that connects to regional clock network
To fix In Ti35, Ti60 FPGAs, the PLL's output clock 4 can only drive the regional clock network. You should use the other clock outputs for the serial and parallel clocks.

lvds_rule_rx_config (error)

Message Input name must be configured
To fix Specify a valid pin name.
Message Serial clock name must be configured
To fix When you are using the LVDS deserializer (deserialization width greater than 1), you need to specify the serial clock pin name.
Message Parallel clock name must be configured
To fix When you are using the LVDS deserializer (deserialization width greater than 1), you need to specify the parallel clock pin name.

lvds_rule_rx_distance (warning)

Message These HSIO GPIO must be placed at least 1 pair away from LVDS <name> in order to avoid noise coupling from GPIO to LVDS: <violated list>
To fix When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO pins between any GPIO and HSIO used as LVDS RX in the same bank. This separation reduces noise.

lvds_rule_rx_dpa (error)

Message Half-rate deserialization is not supported with DPA delay mode
To fix You can only use full-rate serialization with DPA mode. Turn off the Enable Half Rate Deserialization option.

lvds_rule_rx_dpa_es_device (error)

Message DPA delay mode is not supported in ES device
To fix The ES FPGA does not support DPA.

lvds_rule_rx_dpa_data_rate (info)

Message

DPA usage on data rate < 800Mbps is not significant. DPA might not find an optimum step to lock, dis-enable DPA and assume DPA has locked when DLY_DBG stepped on 0 or 63. Refer to AN 044 for more info.
To fix Data rates below 800 Mbps can result in a rolloff or overflow in the value of DLY_DBG, which in turn can cause a jump directly from 0 to 63, or 63 to 0. Such a rolloff invalidates the DPA operation. Refer to "Calibrating with Dynamic Phase Alignment (DPA) (Titanium/Topaz only)" in AN 044: Aligning LVDS Clock and Data.

lvds_rule_rx_dpa_serial (error)

Message DPA delay mode is not supported with deserialization disabled
To fix You cannot use dynamic phase alignment in bypass mode.
Message DPA delay mode is not supported with deserialization width less than 3
To fix You cannot use dynamic phase alignment with x1 or x2 modes.

lvds_rule_rx_empty_pins (error)

Message Empty pin names found: <list>
To fix You need to specify the pin names listed in the message.

lvds_rule_rx_fifo (error)

Message Clock Crossing FIFO is not supported with deserialization width <1/2>
To fix The Clock Crossing FIFO is only available for deserialization widths > 2. Disable the Clock Crossing FIFO or change the serialization value.
Message Clock Crossing FIFO is only supported with deserialization enabled
To fix The Clock Crossing FIFO is only available for deserialization widths > 2. Disable the Clock Crossing FIFO or change the serialization value.

lvds_rule_rx_param (error)

Message Invalid parameters configuration: <list>
To fix One of the parameters you set was incorrect. Review any other errors for details.

lvds_rule_rx_pll_refclk (error)

Message Serial clock name is not a PLL output clock
To fix Use a PLL output clock as the serial (FASTCLK) clock.
Message Parallel clock name is not a PLL output clock
To fix Use a PLL output as the parallel (SLOWCLK) clock.

lvds_rule_rx_pll_refclk (warning)

Message Serial clock is expected to be from the following PLL instance: <resource>
To fix Only a specific PLL instance can drive the LVDS RX clocks. Change the PLL to use that resource. See PLL Requirements for Serial and Parallel Clocks.
Message PLL driving the serial clock should have its reference clock from an LVDS in pll_clkin connection type
To fix The PLL's reference clock needs to be driven by a specific resource. Create an LVDS RX block and set the Connection Type to pll_clkin. Then use that block as the PLL reference clock.
Message Parallel clock is expected to be from the following PLL instance: {}
To fix Only a specific PLL instance can drive the LVDS RX clocks. Change the PLL to use that resource. See PLL Requirements for Serial and Parallel Clocks.
Message PLL driving the parallel clock should have its reference clock from an LVDS in pll_clkin connection type
To fix The PLL's reference clock needs to be driven by a specific resource. Create an LVDS RX block and set the Connection Type to pll_clkin. Then use that block as the PLL reference clock.

lvds_rule_rx_serial_width (error)

Message Unsupported deserializaion width: 9
To fix The LVDS block does not support a deserialization wiudth of 9. Choose another width.

lvds_rule_tx_width_1or2 (error)

Message Parallel clock name is required with serialization width 2
Serialization width <1/2> only requires the parallel clock name to be specified
To fix When you are using the LVDS serializer (serialization width greater than 1), you need to specify the parallel clock pin name.

lvds_rule_rx_width_1or2 (error)

Message Parallel clock name is required with deserialization width 2
Deserialization width <1/2> only requires the parallel clock name to be specified
To fix When you are using the LVDS deserializer (serialization width greater than 1), you need to specify the parallel clock pin name.

lvds_rule_serial_rate (error)

Message Half rate serialization only allowed with even serialization width
To fix When you turn on Enable Half Rate Serialization, you can only use an even number for the serialization width. Change the width to an even number or turn the option off.

lvds_rule_tx_clock (error)

Message Serial and parallel clocks cannot be the same clock
To fix You cannot use the same clock for both the serial (FASTCLK) and parallel (SLOWCLK) clocks.
Message Serial clock name is not a PLL output clock
To fix Use a PLL output clock as the serial (FASTCLK) clock.
Message Parallel clock name is not a PLL output clock
To fix Use a PLL output as the parallel (SLOWCLK) clock.
Message Serial and parallel clocks are not from the same PLL instance
To fix You need to use the same PLL to generate both clocks.
Message Invalid phase shift difference: <phase shift difference> = Serial: <serial clk shifted time> - Parallel: <parallel clk shifted time> (max=<max shift difference allowed>, min=<min shift difference allowed>)
To fix Adjust the phase shift for the serial clock and parallel clock to ensure that the phase-shifted time difference falls within the range of 45 to 135 degrees, relative to the phase-shifted time of the serial clock.
Message Serial clock frequency has to be <float> times faster than parallel clock
To fix Make sure that the PLL output clock frequencies are set correctly.
Half rate calculation—serial clock frequency = parallel clock frequency * (serialization / 2)
Full rate calculation—serial clock frequency = parallel clock * serialization
Message Invalid phase shift difference: {phase shift difference} = Serial: {serial clk shifted time} - Parallel: {parallel clk shifted time} (max={max shift difference allowed}, min={min shift difference allowed)
Example: Invalid phase shift difference: 0.0000 ps = Serial: 400.0000 ps = Parallel: 400.0000 ps (max=600.0000 ps, min = 200.0000 ps)
To fix

Adjust the phase shift for the serial clock and parallel clock to ensure that the phase-shifted time difference falls within the specified range.

lvds_rule_tx_clock_region (error)

Message Serial and Parallel clocks generated by PLL have to be driven to the same clock network. <Serial | Parallel> clock <name> was generated by PLL output clock 4 that connects to regional clock network
To fix In Ti35, Ti60 FPGAs, the PLL's output clock 4 can only drive the regional clock network. You should use the other clock outputs for the serial and parallel clocks.

lvds_rule_tx_distance (error)

Message These HSIO GPIO must be placed at least 1 pair away from LVDS <name> in order to avoid noise coupling from GPIO to LVDS: <violated list>
To fix When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO pins between any GPIO and HSIO used as LVDS TX in the same bank. This separation reduces noise.

lvds_rule_tx_empty_pins (error)

Message Empty pin names found: <list>
To fix You need to specify the pin names listed in the message.

lvds_rule_tx_param (error)

Message Invalid parameters configuration: <list>
To fix One of the parameters you set was incorrect. Review any other errors for details.

lvds_rule_tx_serial_width (error)

Message Unsupported serializaion width: 9
To fix The LVDS block does not support a serialization wiudth of 9. Choose another width.

lvds_rule_tx_vref (error)

Message This resource is reserved as vref for bank <name>. Us a different resource to configure LVDS Tx custom output differential type
To fix Some resources can be used as the VREF for an I/O standard. If you are using an I/O standard that uses a VREF pin, you must use this resource as a VREF. Choose another resource for the LVDS function.
Message GPIO <name> has to be configured as vref input mode to support LVDS Tx custom output differential type
GPIO <name> has to be configured as vref input to support LVDS Tx custom output differential type
To fix If you are using an I/O standard that uses a VREF pin, you must use this resource as a VREF. Configure the GPIO as an input and choose vref as the Connection Type.
Message LVDS Tx custom output differential type cannot be used due to unbonded vref resource on the same bank <bank>
LVDS Tx custom output differential type cannot be used due to vref resource not bonded out
To fix If a VREF pin is not available in the I/O bank (e.g., it is not in the FPGA/package you chose), you cannot use an I/O standard that requires it. Instead choose a different I/O standard or a different resource.

lvds_rule_clkout_ser_disabled (error)

Message Output clock name must be configured in clock output mode with serialization disabled
To fix Specify the output clock name.

lvds_rule_rx_pll_feedback (warning)

Message PLL <pll_slow_inst_name> driving the LVDS Rx clock sources should have its feedback mode set to core for optimized performance
To fix Set feedback mode of the PLL to core for better performance.