Interface Blocks

Titanium™ FPGAs support a variety of interface blocks. The available blocks differ depending on which FPGA you target and the package. You need to assign a resource for every block you use.

The following table describes the interface blocks supported in the Efinity® software.

Note: New package support is often added in patches. Refer to the Efinity Release Notes in the Support Center for the latest patch support.
Table 1. Titanium Interface Block Support by Package
Interface Ti35 Ti60 Ti85 Ti90 Ti120 Ti135 Ti165 Ti180 Ti240 Ti375
DDR – – All J361, J484, G529 J361, J484, G529 All All J361 J484, M484, G529 All All
GPIO All All All All All All All All All All
GPIO bus All All All All All All All All All All
HyperRAM F100S3F2 F100S3F2 – – – – – – – –
I/O bank All All All All All All All All All All
JTAG User TAP All All All All All All All All All All
LVDS TX
LVDS RX
Bidirectional LVDS
 All All All All All All All All All All
MIPI DPHY – – All J361, J484, L484 J361, J484, L484 All N484, N900, N1156 J361, J484, L484, M484, J484D1 N484, N900, N1156 N484, N900, N1156
MIPI TX Lane
MIPI RX Lane
 All All All All All All All All All All
PCI Express®
Ethernet XGMII
PMA Direct
Ethernet SGMII
 – – All – – All N484, N900, N1156 – N484, N900. N1156 N484, N900, N1156
PLL (V3) All All – All All – – All – –
PLL (Fractional) – – All – – All All – All All
PLL SSC – – All J361, J484, L484 J361, J484, L484 All N484, N900, N1156 J361, J484, L484, M484 N484, N900, N1156 N484, N900, N1156
Oscillator All All All All All All All All All All
Quad-Core RISC-V – – All – – All All – All All
SPI Flash F100S3F2 F100S3F2 – – – N576D2F4 – – – –

All interface blocks have an instance name that must be a unique identifier. When you add a new block, the Interface Designer gives the block a unique default name, which you can change.

Note: After you re-name the block, press Enter or click Save to save the name.

Pin names are the top-level ports of the design implemented in the core that connect to the interface block. These names must be legal Verilog HDL or VHDL identifiers.