Create an LVDS RX Interface with PHY Clock

About this task

The following figure shows a completed LVDS RX interface, where n is the deserialization width and m is the number of RX lanes.

Follow these steps to build an LVDS RX interface using the Efinity® Interface Designer.

Add an LVDS / SLVS RX block to act as the PLL reference clock input:

Option	Description
LVDS Type	Receiver (RX)
LVDS Resource	Choose a valid resource.
Connection Type	pll_clkin
Input Pin/Bus Name	Use the clock LVDS RX clock output name as the incoming clock.

Add a PLL block with the following settings:

Option	Description
Resource	Choose a PLL resource.
Reference Clock Mode	External
Reference Clock Frequency	Set the reference clock frequency to match the clock coming from the LVDS RX reference clock you created in step 1.
Output Clock	For LVDS deserializer widths 2 - 10, define the output clocks so that you have one for the fast clock (serial) and one for the slow clock (parallel). Set the relationship between the clocks as serial clock frequency = parallel clock frequency * (deserialization / 2) (half rate) or serial clock frequency = parallel clock * deserialization (full rate). The serial clock pahase shift should be between 45 and 135 degrees.

Add an LVDS RX block with these settings:

Option	Description
LVDS Type	Receiver (RX)
LVDS Resource	Any channel
Enable Deserialization	On
Deserialization Width	n
Half Rate	If using half-rate serialization, turn on Enable Half-Rate Serialization.
Output Pin/Bus Name	Any
Serial Clock Pin Name	Use the fast clock output name that corresponds to the PLL you chose.
Parallel Clock Pin Name	Use the slow clock output name that corresponds to the PLL you chose.