MIPI Groups by Package

You can use multiple HSIO as MIPI D-PHY lanes to build complete MIPI interfaces with one clock lane and up to 8 data lanes.

For MIPI TX interfaces, you can use any lane anywhere on the FPGA.
For MIPI RX interfaces, the number of data lanes is restricted by the number of lanes in the MIPI group. These groups vary depending on the package.

The Resource Assigner shows the MIPI RX group in the Block Summary's Feature field.

Notice: To view the MIPI RX groups for each package graphically, go to the Titanium Packaging User Guide.