Implementing a Zero-Delay Buffer

Titanium PLLs can implement a zero-delay buffer circuit. In this mode, the PLL removes all of the clock-insertion delay from the input I/O buffer and core clock tree. You may want to use this buffer when you have a single clock signal that fans out to more than one destination with low skew.

To implement a zero-delay buffer:

  • In the PLL Clock Calculator, use Feedback Mode > External.
  • Add a GPIO for the clock output.
  • Add a second GPIO for the external feedback.
  • Add a third GPIO for the PLL reference clock.
  • On your board, connect the clock output pin to the external feedback pin.

Figure 1. Zero-Delay Buffer Block Diagram

The following code example shows an .isf that implements a zero-delay buffer for the Ti60 F225.

# Efinity Interface Configuration
# Version: 2021.1.165.2.19
# Date: 2021-09-23 15:23
#
# Copyright (C) 2017 - 2021 Efinix Inc. All rights reserved.
#
# Device: Ti60F225
# Package: 225-ball FBGA (preliminary)
# Project: r4000
# Configuration mode: active (x1)
# Timing Model: C4 (preliminary)

# Create instance
design.create_clockout_gpio("clkout")
design.create_pll_ext_fb_gpio("fbk_clk")
design.create_pll_input_clock_gpio("ref_clk")
design.create_block("pll_inst1","PLL")

# Set property, non-defaults
design.set_property("clkout","OUT_CLK_PIN","clk")
design.set_property("pll_inst1","CLKOUT0_EN","1","PLL")
design.set_property("pll_inst1","CLKOUT1_EN","0","PLL")
design.set_property("pll_inst1","CLKOUT2_EN","0","PLL")
design.set_property("pll_inst1","CLKOUT3_EN","0","PLL")
design.set_property("pll_inst1","CLKOUT4_EN","0","PLL")
design.set_property("pll_inst1","REFCLK_SOURCE","EXTERNAL","PLL")
design.set_property("pll_inst1","CLKOUT0_DIV","82","PLL")
design.set_property("pll_inst1","CLKOUT0_DYNPHASE_EN","0","PLL")
design.set_property("pll_inst1","CLKOUT0_PHASE_SETTING","0","PLL")
design.set_property("pll_inst1","CLKOUT0_PIN","clk","PLL")
design.set_property("pll_inst1","EXT_CLK","EXT_CLK0","PLL")
design.set_property("pll_inst1","LOCKED_PIN","","PLL")
design.set_property("pll_inst1","M","1","PLL")
3design.set_property("pll_inst1","N","1","PLL")
4design.set_property("pll_inst1","O","2","PLL")
design.set_property("pll_inst1","OUTPUT_CLOCKS_INVERTED","0","PLL")
design.set_property("pll_inst1","PHASE_SHIFT_ENA_PIN","","PLL")
design.set_property("pll_inst1","PHASE_SHIFT_PIN","","PLL")
design.set_property("pll_inst1","PHASE_SHIFT_SEL_PIN","","PLL")
design.set_property("pll_inst1","REFCLK_FREQ","33.33","PLL")
design.set_property("pll_inst1","RSTN_PIN","","PLL")
design.set_property("pll_inst1","FEEDBACK_MODE","EXTERNAL","PLL")
design.set_property("pll_inst1","FEEDBACK_CLK","CLK0","PLL")

# Set resource assignment
design.assign_pkg_pin("clkout","M7")
8design.assign_pkg_pin("ref_clk","P2")
9design.assign_pkg_pin("fbk_clk","R6")
10design.assign_resource("pll_inst1","PLL_BL0","PLL")