Design Check: Clock Control Messages

When you check your design, the Interface Designer applies design rules to your clock and control settings. The following tables show some of the error and warning messages you may encounter and explains how to fix them.

clock_rule_capacity (error)

Message	Cannot connect to more than <int> different clocks per region (40 rows) on left and right and <int> clocks on the top or bottom
To fix	You cannot have more than 32 clocks (GPIO configured in clkout mode) coming from the core. You need to remove some clocks.

Message	Cannot connect to more than <int> different clocks per region (40 rows) on left and right
To fix	You are using more clocks that are available for the local region. Remove some clocks. See "Driving the Local Network" in the data sheet.

Message	Cannot connect to more than <int> different clocks on top and bottom
To fix	You are using more clocks than are available on the top and bottom local regions. Remove some clocks. See "Driving the Local Network" in the data sheet.

clock_rule_max_count (error)

Message	Number of core clock used exceeds max limit of <int>
To fix	You cannot have more than 32 clocks (GPIO configured in clkout mode) coming from the core. You need to remove some clocks.

clock_rule_lvds_bidir_fast_clk_comm (warning)

Message	Some serial clocks used in certain bank instances have a propagation delay that differs from other banks, thereby impacting the subsequent clock: [<fast clock name> (Different propagation bank: <bank_name> Instances: <list of instance name>)]
To fix	You get this warning if you use the same serial clock for LVDS Bidir instances that use resources from different banks. Update the instance’s resource to use resources from the same bank mentioned in the message.

clock_rule_lvds_rx_clock_source (warning)

Message	The following PLL instance has output clocks driving LVDS Rx instance on different sides pair - [<PLL instance>: [<clock name>(<LVDS instance>)]]
To fix	The PLL output clocks go to multiple LVDS RX on different sides of the FPGA. The fast clock and slow clock can only drive I/O from the same left/right or top/bottom sides. For example, TR_PLL generates rx_fastclk and rx_slowclk for LVDS in the right-side bank. These clocks can also drive the LVDS channel on the left bank. However, they cannot drive LVDS in the top or bottom banks.

clock_rule_lvds_rx_fast_clk_comm (warning)

Message	Some serial clocks used in certain bank instances have a propagation delay that differs from other banks, thereby impacting the subsequent clock: [<fast clock name> (Different propagation bank: <bank_name> Instances: <list of instance name>)]
To fix	You get this warning if you use the same serial clock for LVDS RX instances that use resources from different banks. Update the instance’s resource to use resources from the same bank mentioned in the message.

clock_rule_lvds_tx_fast_clk_comm (warning)

Message	Some serial clocks used in certain bank instances have a propagation delay that differs from other banks, thereby impacting the subsequent clock: [<fast clock name> (Different propagation bank: <bank_name> Instances: <list of instance name>)]
To fix	You get this warning if you use the same serial clock for LVDS TX instances that use resources from different banks. Update the instance’s resource to use resources from the same bank mentioned in the message.

clock_rule_mipi_tx_fast_clk_comm (warning)

Message	Some serial clocks used in certain bank instances have a propagation delay that differs from other banks, thereby impacting the subsequent clock: [<fast clock name> (Different propagation bank: <bank_name> Instances: <list of instance name>)]
To fix	You get this warning if you use the same serial clock for MIPI TX instances that use resources from different banks. Update the instance’s resource to use resources from the same bank mentioned in the message.

clock_rule_pll_ref_clock_lvds_rx (error)

Message	The following PLL instance has reference clock that does not match the side of the LVDS Rx instance driven by its output clocks - [<PLL instance>: [<clock name>(<LVDS instance>)]]
To fix	Choose the PLL reference clock that is on the same side as the LVDS that the output clock is driving. For example, if TR_PLL is driving LVDS on the right side, the PLL external source clock should also come from the I/O on the right side.

clock_rule_undefined_name (info)

Message	Clock <clock name> not defined in the interface, assuming core generated.
To fix	All clocks in the periphery must be defined in the Interface Designer (GPIO clock, oscillator, PLL, LVDS GCLK, MIPI D-PHY CLK). This info message indicates that you have not defined it as an interface block. If the clock is generated in the core you can ignore this message.

clkmux_rule_clocks_routed (error)

Message	Unrouted pins driving inputs of clock mux <ins name>:<inputs not routeable> Some inputs of clock mux <ins name> were not routed
To fix	The software tries to route all of the clocks according to the scheme shown in "Driving the Global Network" in the data sheet. If it cannot find a mapping, it issues this error. Reassign the instances to other resources or try using a different PLL output clock (if they are not all assigned).

clkmux_rule_core_clock_pin (error)

Message	Core clock pin can only be used with dynamic mux enabled
To fix	Clocks from the core can only drive the dynamic clock multiplexers (see "Driving the Global Network" in the data sheet). Enable a dynamic mux (0 or 7) and assign the core clock to it (Configuring the Dynamic Clock Multiplexers).

clkmux_rule_core_clock_static_mux (error)

Message	Core clock pin <name> not allowed to route through static mux output
To fix	Clocks that come from the core can only connect to dynamic multiplexer input (see "Driving the Global Network" in the data sheet). You need to add the clock to a dynamic mux.

clkmux_rule_dynamic_clock_pin (error)

Message	Dynamic clock pin names for <both dynamic muxes/dynamic mux 0/7> <are/is> empty
To fix	You need to specify the pin name. Go to Device Setting > Clock/Control Configuration > <region> > Global Buffers tab.

clkmux_rule_dynamic_clock_select_pin (error)

Message	Dynamic clock select pin names for <both dynamic muxes/dynamic mux 0/7> <are/is> empty
To fix	You need to specify the pin name. Go to Device Setting > Clock/Control Configuration > <region> > Global Buffers tab.

clkmux_rule_global_regional_pin (error)

Message	Missing global pin name for a regional connection that also connects to global buffer
To fix	If you want to use a clock source to drive both the global and regional networks, you need to specify the name of the clock that drives the global network. See Driving both the Global and Regional Networks.

Message	Global and regional buffer connections require unique pin name
To fix	If you are using both the global and regional buffers, you need to specify unique pin names for each one.

clkmux_rule_global_regional_resource (error)

Message	Regional buffer resource <name> does not support global connection
To fix	Some clock sources cannot connect to the global network, e.g., PLL CLKOUT4. Look in the Resource Assigner Alt Conn column to find a different resource that can connect.

clkmux_rule_pll_clock (warning)

Message	Dynamic clock mux <ClockMux Name> connected to both inverting and non-inverting clock sources: Clock inversion will not be applied to <Clock Names>
To fix	Disable the clock inversion option in the PLL instance properties for clocks that are connect to the dynamic clock mux.

clkmux_rule_pll_output_clock (error)

Message	Found the following PLL output clock routed multiple times: <PLL output>
To fix	PLL clocks connect to clock muxes on two sides of the device. Only one of these connections may be used at a time. Make sure you have not chosen a PLL clock as a dynamic clock source and enabled it to independently drive the core on two different clock muxes.

clkmux_rule_pll_serial_parallel_clocks (error)

Message	Clock <PLL Resource.CLKOUT#> is not found to be routed on the same side with other PLL clocks: <list of PLL Resources.CLKOUT# that must be on the same side>
To fix	The software tries to route all of the clocks according to the scheme shown in "Driving the Global Network" in the data sheet. If it cannot find a mapping, it issues this error. Reassign the instances to other resources or try using a different PLL output clock (if they are not all assigned).

clkmux_rule_regional_conn_type (error)

Message	Regional buffer instance <name> requires connection type to be set to rclk
To fix	If you are a clock source to drive the reginal network, you need to choose rclk as the Connection Type in the Input tab. (see Input Mode)

clkmux_rule_type_config (error)

Message	Resource <name> configured as MIPI LANE Rx not allowed to connect to dynamic mux <0/7> Resource <name> configured as GPIO/LVDS not allowed to connect to dynamic mux <0/7> Invalid output clock configuration of <name> connected to index <int> of dynamic mux <0/7> Assigned core clock pin name at index <int> of dynamic mux <0/7> is empty Resource <name> assigned to input <int> of dynamic mux <0/7> but no valid configured instance found
To fix	You get this error if you have not configured the clock source correctly to connect to the dynamic mux. For example, you can configure the same resource as GPIO, LVDS, or a MIPI lane. If you configure it as a MIPI lane, then you cannot connect it to the dynamic mux. Only GPIO or LVDS can connect. See "Driving the Global Network" in the data sheet for the sources that can drive the dynamic multiplexer.

Message	Resource <name> with instance <name> assigned to RBUF# has invalid configuration Resource <name> with instance <name> can only connect to regional buffer input # through output clock 4
To fix	You can only connect the PLL output to regional buffers on the top and bottom. Refer to "Driving the Regional Network" in the data sheet.

pma_clkmux_rule_clocks_routed (error)

Message	Unrouted pins driving inputs of pma clock mux <instance name>:<inputs not routeable>. Please refer to the summary report and device datasheet Clock Network section for more details.
To fix	Change the transceiver-related instances to other resources or use an rclk connection type for the clock.

Message	Some inputs of pma clock mux <instance name> were not routed
To fix	The software tries to route all of the clocks according to the scheme shown in "Driving the Global Network" in the data sheet. If it cannot find a mapping, it issues this error. Reassign the instances to other resources or try using a different PLL output clock (if they are not all assigned).