Clock and Control Networks

The clock and control network is distributed through the FPGA to provide clocking for the core's LEs, memory, DSP blocks, I/O blocks, and control signals. The FPGA has global signals that can be used as either clocks or control signals. The global signals are balanced trees that feed the whole FPGA.

The FPGA also has regional signals that can only reach certain FPGA regions, including the top or bottom edges. The FPGA has regional networks for the core, right interface, and left interface blocks. The top and bottom interface blocks have one regional clock network each. You can drive the right and left sides of each region independently. Each region also has a local network of clock signals that can only be used in that region.

The core's global buffer (GBUF) blocks drive the global and regional networks. Signals from the core and interface can drive the GBUF blocks.

Each network has dedicated enable logic to save power by disabling the clock tree. The logic dynamically enables/disables the network and guarantees no glitches at the output.

Figure 1. Global and Regional Clock Network Overview (Ti35, Ti60)

Figure 2. Global and Regional Clock Network Overview (Ti90, Ti120, Ti180)

Figure 3. Global and Regional Clock Network Overview (Ti85, Ti135)

Figure 4. Global and Regional Clock Network Overview (Ti165, Ti240, Ti375)

Note: For detailed descriptions of the clock networks, refer to the data sheet.