Using the DDR Interface

The following tables describe the settings for the Titanium DDR block in the Interface Designer. (See which packages support DDR.)

Table 1. Base Tab
Parameter Choices Notes
Instance Name User defined Indicate the DDR instance name. This name is the prefix for all DDR signals.
DDR Resource None, DDR_0, DDR_1 Indicate the resources available.
Data Width 16, 32 Choose the DQ width. Default: 32 (16 for J361 and M484 packages)
Memory Density 2G, 3G, 4G, 6G, 8G, 12G, 16G Choose the memory density per channel. Default: 4G
Physical Rank 1, 2 Default: 1
Memory Type LPDDR4/4X Default: LPDDR4
Clock CLKIN 0, CLKIN 1, CLKIN 2 Choose which PLL resource to use as the DDR clock.
CLKIN 0—PLL_TL0
CLKIN 1—PLL_TL1
CLKIN 2—PLL_TL2 (default)
Table 2. Advanced Options Tab (FPGA Settings)Perform IBIS simulation to determine which settings are the most suitable for your application. IBIS models are available in the Efinix Support Center.
Option Choices Notes
DQ Pull-Down Drive Strength (Ohm) 34.3, 40, 48, 60, 80, 120, 240 Default: 48
DQ Pull-Down ODT (Ohm) 34.3, 40, 48, 60, 80, 120, 240, High-Z Default: 60
DQ Pull-Up Drive Strength (Ohm) 34.3, 40, 48, 60, 80, 120, 240 Default: 48
DQ Pull-Up ODT (Ohm) 34.3, 40, 48, 60, 80, 120, 240, High-Z Default: High-Z
VREF Range Selection Range 0, Range 1 Default: Range 0
VREF Setting (% of VDDQ) LPDDR4, Range 0:
5.40 - 38.42 (step: 0.26)
LPDDR4, Range 1:
11.90 - 48.222 (step: 0.286)
LPDDR4x, Range 0:
11.60 - 49.70 (step: 0.3)
LPDDR4x, Range 1:
21.20 - 59.30 (step: 0.3)
 Default:
LPDDR4, Range 0: 21.78
LPDDR4, Range 1: 29.918
LPDDR4x, Range 0: 30.5
LPDDR4x, Range 1: 40.1
Table 3. Advanced Options Tab (Memory Mode Register Settings)
Option Choices Notes
Burst Length BL = 16 Sequential,
BL = 16 or 32 Sequential,
BL = 32 Sequential		 Default: 16 Sequential
CA Bus Receiver On-Die-Termination for CS0/CS1 Disable, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6 Default: Disable
DQ Bus Receiver On-Die-Termination for CS0/CS1 Disable, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6 Default: Disable
Pull-Down Drive Strength (PDDS) for CS0/CS1 RFU, RZQ/1, RZQ/2, RZQ/3, RZQ/4, RZQ/5, RZQ/6 Default: RZQ/6
CA VREF Setting Range Selection RANGE [0], RANGE [1] Default: RANGE [1]
CA VREF Settings (% of VDD2) RANGE [0]:
10 - 30 (step: 0.4)
RANGE [1]:
22 - 42 (step: 0.4)
 Default:
RANGE [0]: 27.2
RANGE [1]: 27.2
DQ VREF Setting Range Selection RANGE [0], RANGE [1] Default: RANGE [1]
DQ VREF Settings (% of VDDQ) RANGE [0]:
10 - 30 (step: 0.4)
RANGE [1]:
22 - 42 (step: 0.4)
 Default:
RANGE [0]: 27.2
RANGE [1]: 27.2
Enable DBI Write On or off Enable data bus inversion (DBI) for write operation.
When enabled, the controller automatically inverts the write data byte if there are 5 or more '1's in the data bus, and indicates the data is inverted by driving the DDR_DM signal high.
Default: On
Enable DBI Read On or off Enable data bus inversion (DBI) for read operation.
When enabled, the controller automatically inverts the read data byte if the DDR_DM signal is high.
Default: On
CK ODT CS0/CS1 Enabled for Non-terminating Rank Override Disabled, Override Enabled Default: Override Disabled
CS ODT CS/CS1 Enabled for Non-terminating Rank Override Disabled, Override Enabled Default: Override Disabled
CA ODT CS/CS1 Termination Disable Obeys ODT_CA Bond Pad, Disabled Default: Override Obeys ODT_CA Bond Pad
Table 4. Config Controller Tab
Option Choices Notes
<description> Pin Name User defined Configuration and control pins. You can use the default names or specify your own.
Table 5. Advanced Options Tab (Memory Timing Settings)
Option Choices Notes
tCCD, CAS-to-CAS Delay (cycles) 8 - 31 Default: 8
tCCDMW, CAS-to-CAS Delay Masked Write (cycles) 32 - 63 Default: 32
tFAW, Four-Bank Activate Window (ns) 40 - 100 Default: 40
tPPD, Precharge to Precharge Delay (cycles) 4 - 7 Default: 4
tRAS, Row Active Time (ns) 42 - 100 Default: 42
tRCD, RAS-to-CAS Delay (ns) 18 - 100 Default: 18
tRPab, Row Precharge Time (All Banks) (ns) 21 - 100 Default: 21
tRPpb, Row Precharge Time (Single Bank) (ns) 18 - 100 Default: 18
tRRD, Active Bank-A to Active Bank-B (ns) 10 - 100 Default: 10
tRTP, Internal Read To Precharge Delay (ns) 7.5 - 100 Default: 7.5
tSR, Minimum Self Refresh Time (ns) 15 - 100 Default: 15
tWR, Write Recovery Time (ns) 18 - 60 Default: 18
tWTR, Write-To-Read Delay (ns) 10 - 60 Default: 10
Table 6. AXI 0 and AXI 1 Tabs
Parameter Choices Notes
Enable Target 0
Enable Target 1
 On or off Turn on to enable the AXI 0 interface.
Turn on to enable the AXI 1 interface.
AXI Clock Input Pin Name User defined Specify the name of the AXI input clock pin.
Invert AXI Clock Input On or off Turn on to invert the AXI clock.
AXI Reset Pin Name User defined Specify the name of the AXI reset clock pin or use the default.
Read Address Channel tab
Write Address Channel tab
Write Response Channel tab
Read Data Channel tab
Write Data Channel tab
 User defined These tabs defines the AXI signal names for the channels. Efinix recommends that you use the default names.
Table 7. Controller Status Tab
Option Choices Notes
Invert Controller Status Clock Pin On or off Turn on if you want to invert the clock.
Default: off
<description> Pin Name User defined Controller status pins. You can use the default names or specify your own.

Table 8. Pin Swizzling Tab
Option Choices Notes
Enable Package Pin Swapping On or off Turn on if you want to swap package pins.
Default: off
DQ/DM Pin Swizzle Groupn – Drag and drop pins in the DRAM column to swap DQ/DM pins.
DQ Width = 16 : n is 0 and 1
DQ Width = 32 : n is 0, 1, 2 and 3
Address Pin Swizzle – Drag and drop pins in the DRAM column to swap address pins.