Driving both the Global and Regional Networks

In some situations you may want a clock source to drive both the global and regional clock networks. In this case, you use the rclk connection type. To drive both a regional and a global, make these settings in the Interface Designer:

1. Create your clock source (e.g., a GPIO).
2. For the Connection Type, choose rclk.
3. In the Resource Assigner, assign a resource that has RCLK shown as an alternate connection.
4. Note the letter after GPIO in the resource name. This letter indicates the side of the FPGA. GPIOB = bottom, GPIOT = top, etc.
5. Click Device Setting > Clock/Control Configuration.
6. Select the bottom, left, right, or top as determined in step 4.
7. Click the Regional Buffers tab.
8. Choose the regional buffer according to "Driving the Regional Network" in the data sheet. When you select a buffer, the resource for that buffer displays under Assignment.
9. Specify a Global Pin Name to drive the global network.