Using the LVDS Block

The LVDS block defines the functionality of the LVDS pins. You can choose whether the block is a transmitter (TX), receiver (RX), or bidirectional.

LVDS TX

Table 1. LVDS TX Options
Option Choices Description
Instance Name User defined Enter a name.
LVDS Resource Resource list Choose a resource.
Output Differential Type lvds Use for LVDS, RSDS, and mini-LVDS.
sublvds Use for subLVDS.
slvs Use for SLVS.
custom Choose this option when you want to use a VREF pin to specify the differential.
Set the GPIO input connection type to vref.
Choose a GPIO pin with that supports VREF in the same bank as the LVDS TX resource.
Output Differential, VOD Typical, large, small The actual voltage depends on this setting and the diffential type and is shown in the Block Summary Value field.
Output-Pre-Emphasis high, medium-high, medium-low, low Choose an output pre-emphasis setting.
Mode serial data output Use the transmitter as a simple output buffer or serialized output.
reference clock output Use the transmitter as a clock output.
Specify the serial and parallel clocks.
When choosing this mode, the serialization width should match the serialization for the rest of the LVDS bus.
Output Pin/Bus Name User defined Output pin or bus that feeds the LVDS transmitter parallel data. The width should match the serialization factor.
Output Enable Pin Name User defined Use with serial data output mode.
Enable Serialization Off Use as a simple buffer.
On Use as an LVDS serializer:
  • Optionally enable half rate serialization.
  • Choose a value of 2, 3, 4, 5, 6, 7, 8, or 10 (1 is a simple buffer). A value of 9 is not legal.
  • Specify the serial clock and parallel clock.
  • Specify reset pin name.
Static Mode Delay Setting 0 - 63 Choose the amount of static delay, each step adds approximately 25 ps of delay.
The maximum LVDS rate is 1.5 Gbps.
  • Half rate calculation—serial clock frequency = parallel clock frequency * (serialization / 2)
  • Full rate calculation—serial clock frequency = parallel clock * serialization
The serial clock must have a phase shift that is between 45 degrees and 135 degrees. Both clocks must come from the same PLL.

The serial clock (also known as the fast clock) outputs data to the pin, the parallel clock (also known as the slow clock) transfers it from the core. An equation defines the relationship between the clocks. For LVDS TX the parallel clock captures data from the core and the serial clock outputs it to the LVDS buffer.

In half-rate mode, new data is output on both edges of the serial clock, in full rate mode it is only on the rising (positive) edge.

LVDS RX

Table 2. LVDS RX Options
Option Choices Description
Instance Name User defined Enter a name.
LVDS Resource Resource list Choose a resource.
Connection Type normal LVDS RX function.
pll_clkin Alternate function. Use as PLL reference clock.
pll_extfb Alternate function. Use as PLL external feedback.
gclk Alternate function. Use as global clock.
rclk Alternate function. Use as regional clock.
Input Pin/Bus Name User defined Input pin or bus that feeds the LVDS transmitter parallel data. The width should match the deserialization factor.
Dynamic Enable Pin Name User defined Dynamically enables or disables the LVDS RX buffer. Disabling the buffer can reduce power consumption when the pin is not in use.
Enable Common Mode Driver On, off If you implement an AC coupled connection, turn on this option. For a typical DC coupled connection, leave this option off.
Enable SLVS On, off Turn on to use SLVS instead of LVDS.
Termination on, off, dynamic For dynamic, specify the pin that controls the dynamic termination.
Enable Deserialization Off Use as a simple buffer.
On Use as an LVDS deserializer:
  • Optionally enable half rate serialization.
  • Choose a width of 2, 3, 4, 5, 6, 7, 8, or 10 (1 is a simple buffer). A width of 9 is not legal.
  • Specify the serial clock and parallel clock.
  • Optionally turn on Enable Clock Crossing FIFO, which uses a FIFO to cross between the slow clock and the user core clock. Specify the FIFO read, clock, and empty pin names.
Delay Mode static Integer from 0 - 63. Each step adds approximately 25 ps of delay.
dynamic Specify the pin names to control the dynamic delay.
dpa Dynamic phase alignment automatically sets the delay value.

The serial clock (also known as the fast clock) captures data from the pin, the parallel clock (also known as the slow clock) transfers it to the core. An equation defines the relationship between the clocks.

The maximum LVDS rate is 1.5 Gbps.
  • Half rate calculation—serial clock frequency = parallel clock frequency * (deserialization / 2)
  • Full rate calculation—serial clock frequency = parallel clock * deserialization
The serial clock must have a phase shift that is between 45 and 135 degrees. Both clocks must come from the same PLL.

LVDS Bidirectional

The LVDS bidirectional block has the same options and choices as the LVDS RX and TX blocks.

Important: You must use the same value for the serialization/deserialization.

PLL Requirements for Serial and Parallel Clocks

With Titanium FPGAs, you need to use the output clocks from specific PLLs as the LVDS serial and parallel clocks.

Table 3. PLL Requirements
FPGA Side PLL
Ti35, Ti60, Ti60ES
 Left BL_PLL, TL_PLL
Right BR_PLL, TR_PLL
Top TR_PLL, TL_PLL
Bottom BR_PLL, BL_PLL
Notice: Refer to AN 044: Aligning LVDS Clock and Data for more information about aligning the clock and data for LVDS interface in different applications.