Design Check: DDR Messages

When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error messages you may encounter and explains how to fix them.

ddr_rule_resource (error)

Message Resource <name> is not a valid DDR device instance
To fix The resource you specified does not exist. Check whether you have a typo in the resource name.

ddr_rule_resource_excluded (error)

Message Resource <resource> is excluded in Package Planner. Please use another resource
To fix The pins for the affected resource have been excluded in the Package Planner, and cannot be assigned. Remove the excluded setting in the Package Planner or choose another resource.

ddr_rule_invalid_pins (error)

Message Invalid pin names found: <pin names>
To fix The pin name you entered has illegal characters. Rename the pin.

ddr_rule_axi0_empty_pins (warning)

Message Empty pin names found
To fix You get this error when you add the DDR block but have not yet specified the AXI Input Clock Pin Name in the AXI0 tab. If you do not want to use AXI0, turn off the Enable Target 0 option in the AXI0 tab.

ddr_rule_axi1_empty_pins (warning)

Message Empty pin names found
To fix You get this error when you add the DDR block but have not yet specified the AXI Input Clock Pin Name in the AXI1 tab. If you do not want to use AXI0, turn off the Enable Target 1 option in the AXI1 tab.

ddr_rule_ctrl_reg_empty_pins (warning)

Message Empty pin names found
To fix You get this error when you add the DDR block but have not yet specified the Controller Status Clock Pin Name in the Controller Status tab.

ddr_rule_config_empty_pins (error)

Message Empty pin names found
To fix If you have names for any of the pins CFG_DONE, CFG_START, CFG_RESET, or CFG_SEL in the Config Controller tab, then you must have names for all of them. CFG_PHY_RSTN is optional.

ddr_rule_controller_clk (error)

Message Clock to Controller pin name need to be specified with use of other Controller pins
To fix You need to enter a name in the Controller Status tab > Controller Status Clock Pin Name field.

ddr_rule_reset_pin (error)

Message Both Reset DDR PHY and Controller Reset pin names need to be specified if used
To fix Enter both pin names.

ddr_rule_pll_feedback (error)

Message Feedback mode for PLL <name> can only be set to local when DDR is configured
To fix You cannot use core or external modes. Change the mode in the PLL Clock Calculator.

ddr_rule_phy_clock (error)

Message Output clock 4 in PLL resource <res_name> for PHY Clock not configured
To fix
Use PLL_TL2 CLKOUT4 to drive the DDR controller.

ddr_rule_phy_clock (warning)

Message PLL clock driving DDR with non-external clock source is not recommended
To fix

You get this warning if you do not connect the reference clock to an I/O pad. The PLL reference clock must be driven by I/O pads. (Using the clock tree may induce additional jitter and degrade the DDR performance.)

ddr_rule_ref_clock_freq (warning)

Message PLL output frequency driving DDR is <#>MHz (max: <#>MHz)
To fix Change the setting for the PLL output clock so that the frequency is lower than that maximum range.

ddr_rule_data_width (error)

Message Selected Data Width <#> is not supported in device
To fix The data width is dependent on the FPGA and package you choose. Refer to the data sheet to see which packages support the data width you want to use.

ddr_rule_clk_conn_type (error)

Message Connection type of PLL <pll instance name> with output clock <pll outclk pin name> that is driving DDR cannot be set to rclk
To fix Change the connection type of the PLL output clock to gclk.

ddr_rule_pll_output_clock (error)

Message PLL Output clock <clk_num> phase shift should be 0 when DDR is configured
To fix Set the PLL output clock <clk_num> phase shift to 0.
Message Output clock 3 for PLL <pll_inst_name> should be used for configuring the high speed DDR clock
To fix Enable the PLL's output clock 3.
Message Frequency output clock 3 for PLL <pll_inst_name> should be 2 * Frequency of output clock 4
To fix Change the PLL's output clock 3 and 4 frequencies so that output clock 3 frequency = 2 * output clock 4 frequency.

ddr_rule_pin_swap (error)

Message Invalid pin name is set for DQ/DM Pin Swizzle (Group<#>: <list of invalid DQ/DM pin names>)
To fix You get this error if you manually edit the <project>.peri.xml file wrongly. The DQ and DM pin names must be DQ<#> or DM<#> respectively.
Message DQ/DM Pins has been used. (Group<#>: <list of invalid DQ/DM pin names>)
To fix You get this error if you manually edit the <project>.peri.xml file wrongly. You cannot use more than one similar DQ/DM pin.
Message Invalid pin name is set for Address Pin Swizzle. (FPGA: <list of invalid CA pin names>)
To fix You get this error if you manually edit the <project>.peri.xml file wrongly. The CA pin names must be CA<#>.
Message Address pin has been used. (FPGA: <list of invalid CA pin names>)
To fix You get this error if you manually edit the <project>.peri.xml file wrongly. You cannot use more than one similar CA pin.

ddr_rule_pll_non_frac (error)

Message PLL {pll_inst_name} driving DDR should disable fractional mode
To fix Disable fractional mode for the PLL instance driving the DDR instance's clock source.
Message Found {number of pins} DDR pin driven by PLL in fractional mode: {Pin names}
To fix Disable fractional mode for the PLL instance driving those pins connected to DDR instance's AXI clock input.