PLL Interface
Efinix FPGAs have one or more PLLs to generate clock frequencies. The number of PLLs and the PLL features vary depending on the family and FPGA.
| PLL Version | Description | Available In |
|---|---|---|
| PLL V3 | Full-featured PLL | Titanium Ti35, Ti60, Ti90, Ti120, and Ti180 FPGAs. |
| FPLL V1 | Fractional PLL | Titanium Ti85, Ti135, Ti165, Ti240, and Ti375 FPGAs. |
| PLL SSC | Spread-spectrum clocking PLL | Titanium FPGAs that have a hardened MIPI D-PHY interface. |
Note: Vx refers to the version number. This number is used to reference the PLL in
the Efinity Python API and interface primitives.