Revision History

Added PCIe root port, slot capability, and hot plug descriptions.

The lvds_rule_rx_distance message is changed from an error to a warning. (DOC-2833)

Added more PCIe messages in Design Check: PCI Express Messages. (DOC-2833)

Corrected instructions in Create an LVDS TX Interface with GCLK or RCLK and Create an LVDS RX Interface with GCLK or RCLK. (DOC-2736)

In Design Check topics, added message about excluded pins. (DOC-2739)

Removed Link Port Number from PCI Express Device Capability Tab. (DOC-2593)

When enabling the HSIO dynamic delay, the delay is updated on the rising edge of DLYCLK. (DOC-2531)

Fix typos. (DOC-2537)

The HyperRAM block has five new options to set the drive strength of the clock, reset, chip select, data strobe, and bus signals. (DOC-2570)

Added Design Check message for HyperRAM drive strength check. (DOC-2570)

Updated interface floorplan diagrams.

Ethernet XGMII now supports 5 Gbps speed setting. (DOC-2326)

Updated messages for transceivers (DOC-2503).

Renamed 10GBase-KR interface as Ethernet XGMII. (DOC-2294)

Updated PMA Direct presets. (DOC-2270)

Updated PCI Express settings.

Added pma_direct_rule_data_rate_timing_model design check rule. (DOC-2270)

The clock_rule_lvds_rx_clock_source message is a warning not an error. (DOC-2308)

Ti85 and Ti135 are available in N484 packages.

The PCI Express block requires that you have a valid APB clock. (DOC-2167)

Added new option for PCI Express block (Base tab) about whether to use a reference clock from an on-board crystal. (DOC-2222)

Updated PCI Express messages. (DOC-2222 and DOC-2264)

Added PMA Direct block > Common Properties tab > Clock and Reset sub-tab and new options. (DOC-2224)

Updated PMA Direct messages for new reset pin name rule. (DOC-2224)

Added more preset options for PMA Direct block. (DOC-2237)

Changed the pll_rule_feedback_clock message about 0 degree phases for feedback clocks from a warning to an info message. (DOC-2252)

Updated interface diagrams to align with resource naming in Efinity software.

Removed Enable Advanced Peripheral Bus option for PCIe. This option must always be turned on. (DOC-2174)

clock_rule_undefined_name is now an info message not a warning (Design Check: Clock Control Messages) (DOC-2071)

Added warning message for pll_rule_feedback_clock about 0 degreed phases for feedback clocks. (DOC-2036)

Removed PLL IOFBK interface pin.

For 10Gbase-KR, changed GUI name for auto-negotiation to Enable Auto Negotiation (AN) Clause 37. (DOC-2194)

When you enable dynamic delay, the delay is updated on the falling clock edge of DLYCLK. (DOC-2159)

Updated GPIO and LVDS interface pin names (IN to I and OUT to O) to align with primitives. (DOC-2086)

Corrected steps for Create a MIPI TX Interface with GCLK or RCLK. (DOC-2157)

Updated MIPI Lane messages. (DOC-2157)

Added note to create new interface block for PCI Express, 10GBase-KR, and PMA Direct if you have made many option changes. (DOC-2067)

Correct typos.

Added PMA Direct Interface chapter.

Added note that the Enable User Status Pin option is only available for FPGAs with transceivers. (DOC-2085)

Enable KR Base option moved to Pins > Control tab. (DOC-2026)

Added floorplan diagram for N676 package.

Updated table of interface blocks and package/interface support matrix.

Updated Design Check: SEU Messages messages.

Updated Design Check: Configuration Messages.

Added N484 and N1156 interface floorplan figures. (DOC-1808) Updated C529 interface floorplan figure.

Added reset recommendations for PLLs and cascaded PLLs. (DOC-1900)

Clarified which signals are available when LVDS settings are enabled. (DOC-1908)

Removed M361 and F529 packages for Ti180 FPGAs.

Added Titanium F100 and F256 packages to interface floorplans.

Added F100 and F256 packages for Ti35 and Ti60 FPGAs in Table 1.

Added HyperRAM for Ti35 and Ti60 in F100S3F2 packages to Table 1.

Updated description for HSIO block DLY_INC signal. (DOC-1697)

Corrected OUTCLK connection in Figure 1. (DOC-1630)

Added 1.35 V HSIO support for Ti135, Ti240, and Ti375.

Added fractional PLL content.

Combined all PLL topics into a single chapter.

Added hardened RISC-V block content.

Added topic on clocking interface blocks. (DOC-1412)

Removed the figures for the emulated MIPI groups by package. Instead refer to the Titanium Packaging User Guide.

Added Drive Strength setting and design checks for HyperRAM block. (DOC-1444)

Added DDR interface Pin Swizzling options and updated DDR design checks. (DOC-1445)

Updated GPIO and LVDS block design checks. (DOC-1481)

Added slvs option for HSIO configured as LVDS blocks. (DOC-1190)

Updated PLL's Invert Output Clock to Output Clock Inversion option which allows the inversion of output clock individually. (DOC-941)

Updated SPI Flash Interface Designer settings. (DOC-1296)

Updated MIPI D-PHY TX Interface Designer settings. (DOC-1178)

Added PLL SSC block. (DOC-1178)

Updated design checks messages for Clock Control, DDR Errors, MIPI DPHY Errors, and PLL Errors.

Updated DDR_DM signal description and added Enable DBI options. (DOC-1322)

Added LVDS RX DBG signals. (DOC-1124)

Updated PLL LOCKED signal description. (DOC-1208)

Added note to state that the PLL tracks the reference clock input frequency accuracy. (DOC-1179)

Added note about using LVDS blocks from the same side of the FPGA to minimize skew. (DOC-1150)

Updated DDR DRAM interface input clock to include description for J361, J484, and G529 packages. (DOC-1209)

Added PLL Interface Designer Settings and updated description for CLKOUT when driving core logic for Ti35 and Ti60 FPGAs. (DOC-1130)

Added DPA to LVDS RX options table. (DOC-922)

Removed DDR block AXI width option. (DOC-1210)

Updated PLL RSTN signal description about de-asserting only when CLKIN is stable. (DOC-1226)

Corrected PLL_SSC_EN MIPI TX D-PHY signal notes. (DOC-1101)

Updated MIPI DPHY TX and DDR Interface Designer Settings.

Updated DDR DRAM Interface Designer Settings.

Updated PLL clock for DDR DRAM block. (DOC-881)

Corrected MIPI RX Lane Block Diagram. (DOC-878)

Removed GCTRL and RCTRL. (DOC-895)

Added topics on Package Planner.

Corrected AWID_x, AWREADY_x, ARADDR_x, and AWADDR_x DDR signals directions and widths. (DOC-907)

Removed PLL_EXTFB from alternative input. (DOC-849)

Corrected the LVDS maximum speed. (DOC-807)

Updated MIPI D-PHY port names. (DOC-782)

Added I/O banks by package information for Ti90, Ti120, and Ti180. (DOC-821)

Updated DDR pad names.

Added M361, L484, M484, and F529 floorplans.

Corrected description for differential TX static programmable delay. (DOC-786)

Updated HyperRAM clock rate and double data rate specs. (DOC-793)

Corrected missing link and added pointer for list of clock sources in Global Buffer Configuration table.

Added Titanium DDR block interface description.

Added Titanium MIPI DPHY interface block description.

HVIO I/O banks support dynamic voltage shifting. (DOC-444)

Added MIPI RX clock groups for F484 package.

Added interface floorplan for F484 package.

New design rules: io_bank_rule_mode_sel, io_bank_rule_dyn_voltage.

Updated label for Ti60 W64 pin A7. (DOC-651)

Updated JTAG mode connection diagram. (DOC-546)

Updated PLL phase-shift descriptions. (DOC-570)

PLL outputs lock on the negative clock edge. (DOC-552)

Added example PLL zero-delay buffer implementation. (DOC-551)

Added an example for the PLL outputs for the Create a MIPI TX Interface topic. (DOC-580)

New design rule: clock_rule_lvds_rx_clock_source. This rule is effective with Efinity patch v2021.1.4.10. (DOC-589)

New design rules: clock_rule_pll_ref_clock_lvds_rx, pll_rule_pll_freq, lvds_rule_tx_clock_region, lvds_rule_rx_clock_region, lvds_rule_rx_dpa_serial, and mipi_ln_rule_tx_clock_region.