SPI Active Mode

Figure 1. SPI Active (x1) Timing Sequence
The waveform shows the perspective from the control block without any optional external pull-up or pull-down resistors connected.
Table 1. Active Mode Timing
Symbol Parameter Frequency Min Typ Max Units
fMAX_M Active mode internal configuration clock frequency. DIV1 52 80 100 MHz
DIV2 26 40 52 MHz
DIV4 13 20 26 MHz
DIV8 6.5 10 13 MHz
fMAX_M_EXTCLK Active mode external configuration clock frequency. – – – 100 MHz
tSU Setup time. Test condition at 1.8 V I/O standard and 0 pF output loading. – – – ns
tH Hold time. Test condition at 1.8 V I/O standard and 0 pF output loading. – 0 – – ns
tDMIN Minimum time between deassertion of CRESET_N to first valid configuration data. – 32 – – μs
Important: The JTAG pins must be inactive during SPI active configuration.
The EXT_CONFIG_CLK pin must be inactive during SPI active configuration if the internal oscillator is selected as the configuration clock source (default).