user_irq (0x2004)
| Bit(s) | Default | Access | Description |
|---|---|---|---|
| [USER_INTERRUPT_NUM:0] | 'h0 | RO | User interrupt request. This register reflects the interrupt status only when both the interrupt source and the corresponding enable mask register are asserted. |
| Bit(s) | Default | Access | Description |
|---|---|---|---|
| [USER_INTERRUPT_NUM:0] | 'h0 | RO | User interrupt request. This register reflects the interrupt status only when both the interrupt source and the corresponding enable mask register are asserted. |