cth_dma_status (0x4028)
| Bit(s) | Default | Access | Description |
|---|---|---|---|
| 31:24 | – | – | Reserved |
| 23:19 | – | – | Reserved |
| 18:14 | – | – | Reserved |
| 13:9 | – | – | Reserved |
| 8:7 | – | – | Reserved |
| 6 | 1'b0 | RW | Status field for descriptors with the Completed flag. This field is
cleared when bit[0] (Run) of the control register transitions from 0 to
1. When the corresponding status logging in the control register is
enabled, this bit is asserted high after the CTH engine completes data transfer for
descriptors with the Completed flag. |
| 5 | 1'b0 | RW | Status field for descriptors with the Stop flag. Same behavior as bit[6],
but for descriptors with the Stop flag. |
| 4 | – | – | Reserved |
| 3 | – | – | Reserved |
| 2 | – | – | Reserved |
| 1 | – | – | Reserved |
| 0 | 1'b0 | RO | CTH engine Busy status. This bit is set to 1 when the CTH engine is
performing data transfer, and cleared to 0 when the engine is idle. |