Ports

Table 1. Interface Bus
Signal Name Direction Description
Global Clock and Reset
axi_clk Input Increase clock frequency to 250 MHz.
apb_clk Input Clock for APB master and slave interfaces, generated by logic. Clock frequency <200 MHz.
dma_rstn Input SGDMA IP asynchronous reset signal, set to 0 for reset.
apb_rstn Input Asynchronous active-low reset for the APB master and slave interfaces.
m_axi4_pcie Bus
m_axi_pcie_awready Input Write address interface ready signal.
m_axi_pcie_awvalid Output Write address interface signal:
1: Valid.
0: Invalid.
m_axi_pcie_awaddr[63:0] Output Address signal line, transmits address information, gives the first address of a burst transaction.
m_axi_pcie_awid[7:0] Output Transaction identifier, used in out-of-order transactions, identifies the write address group; default is 0.
m_axi_pcie_awlen[7:0] Output AXI4 extended burst length supports INCR burst types for 1 to 256 transfers.
m_axi_pcie_awsize[2:0] Output Number of bytes per transfer, related to WDATA width. For example, if WDATA is 32-bit, AWSIZE = log2(32/8) = 2.
m_axi_pcie_wready Input Write data interface ready signal.
m_axi_pcie_wvalid Output Write data interface signal:
1: Valid.
0: Invalid.
m_axi_pcie_wdata[255:0] Output Data signal line, transmits data information.
m_axi_pcie_wdata_par[63:0] Output Reserved.
m_axi_pcie_wstrb[63:0] Output Data bus valid byte control.
For a 32-bit bus, WSTRB = 4'b0010 means data in WDATA[15:8] is valid.
If all 32 bits of WDATA are valid, WSTRB should be 4'b1111.
m_axi_pcie_wlast Output Asserted high to indicate the last data in a burst transaction.
m_axi_pcie_bready Output Write response interface ready signal.
m_axi_pcie_bvalid Input Write response interface valid signal:
1: Valid.
0: Invalid.
m_axi_pcie_bresp[1:0] Input Write response status:
0: OKEY (normal access successful).
1: EXOKEY.
2: SLVERR (slave error).
3: DECERR (decode error, e.g., no slave address).
m_axi_pcie_bresp_par Input Write response status parity.
m_axi_pcie_bid[7:0] Input Transaction identifier.
m_axi_pcie_bid_par Input Transaction identifier parity.
m_axi_pcie_arready Input Read address interface ready signal.
m_axi_pcie_arvalid Output Read address interface valid signal:
1: Valid.
0: Invalid.
m_axi_pcie_araddr[63:0] Output Address signal line, transmits address information.
m_axi_pcie_arid[7:0] Output Read address ID.
m_axi_pcie_arlen[7:0] Output Burst read length, AXI4 extended burst length supports INCR burst types for 1 to 256 transfers.
m_axi_pcie_arsize[2:0] Output Number of bytes per transfer, related to RDATA width.
For example, if RDATA is 32-bit, ARSIZE = log2(32/8) = 2.
m_axi_pcie_rready Output Read data ready signal.
m_axi_pcie_rvalid Input Read data valid signal:
1: Valid.
0: Invalid.
m_axi_pcie_rid[7:0] Input Transaction identifier.
m_axi_pcie_rid_par Input Transaction identifier parity.
m_axi_pcie_rdata[255:0] Input Data signal line, transmits data information.
m_axi_pcie_rdata_par[63:0] Input Reserved.
m_axi_pcie_rresp[1:0] Input Read response, indicates the status of the read transfer.
m_axi_pcie_rresp_par Input Read response parity.
m_axi_pcie_rlast Input Asserted high when the last valid data in a read burst transfer is transmitted.
s_axi4_pcie Bus
s_axi_pcie_awready Output Write data interface ready signal.
s_axi_pcie_awvalid Input Write data valid signal:
1: Valid.
0: Invalid.
s_axi_pcie_awaddr[63:0] Input Address signal line, transmits address information, gives the first address of a burst transaction.
s_axi_pcie_awid[7:0] Input Transaction identifier, used in out-of-order transactions, identifies the write address group.
s_axi_pcie_awlen[7:0] Input AXI4 extended burst length supports INCR burst types for 1 to 256 transfers.
s_axi_pcie_awsize[2:0] Input Number of bytes per transfer, related to WDATA width.
For example, if WDATA is 32-bit, AWSIZE = log2(32/8) = 2.
s_axi_pcie_wready Output Write address interface ready signal.
s_axi_pcie_wvalid Input Write address interface valid signal:
1: Valid.
0: Invalid.
s_axi_pcie_wdata[255:0] Input Data signal line, transmits data information.
s_axi_pcie_wstrb[31:0] Input Data bus valid byte control.
For example, for a 32-bit bus, WSTRB = 4'b0010 means data in WDATA[15:8] is valid.
If all 32 bits of WDATA are valid, WSTRB should be 4'b1111.
s_axi_pcie_wlast Input Asserted high to indicate the last data in a burst transaction.
s_axi_pcie_bready Input Write response interface ready signal.
s_axi_pcie_bvalid Output Write response interface valid signal:
1: Valid.
0: Invalid.
s_axi_pcie_bresp[1:0] Output Write response status:
0: OKEY (normal access successful).
1: EXOKEY.
2: SLVERR (slave error).
3: DECERR (decode error, e.g., no slave address).
s_axi_pcie_bresp_par Output Response parity bit.
s_axi_pcie_bid[7:0] Output Transaction identifier.
s_axi_pcie_bid_par Output Transaction identifier parity.
s_axi_pcie_arready Output Read address interface ready signal.
s_axi_pcie_arvalid Input Read address interface valid signal:
1: Valid.
0: Invalid.
s_axi_pcie_araddr[63:0] Input Address signal line, transmits address information.
s_axi_pcie_arid[7:0] Input Transaction identifier.
s_axi_pcie_arlen[7:0] Input Burst read length, AXI4 extended burst length supports INCR burst types for 1 to 256 transfers. Burst transfers have the following rules:
  • Wrapping burst length must be 2, 4, 8, or 16.
  • Bursts cannot cross 4KB boundaries.
  • Early termination of burst transfers is not supported.
s_axi_pcie_arsize[2:0] Input Number of bytes per transfer, related to RDATA width.
For example, if RDATA is 32-bit, ARSIZE = log2(32/8) = 2.
s_axi_pcie_rready Input Read data ready signal.
s_axi_pcie_rvalid Output Read data interface valid signal:
1: Valid.
0: Invalid.
s_axi_pcie_rid[7:0] Output Transaction identifier.
s_axi_pcie_rid_par Output Transaction identifier parity.
s_axi_pcie_rdata[255:0] Output Data signal line, transmits data information.
s_axi_pcie_rresp[1:0] Output Read response, indicates the status of the read transfer.
s_axi_pcie_rresp_par Output Read response parity.
s_axi_pcie_rlast Output Asserted high when the last valid data in a read burst transfer is transmitted.
m_axi4_user Bus
m_axi_usr_awready Input Write address interface ready signal.
m_axi_usr_awvalid Output Write address interface valid signal:
1: Valid.
0: Invalid.
m_axi_usr_awaddr[63:0] Output Address signal line, transmits address information, gives the first address of a burst transaction.
m_axi_usr_awid[7:0] Output Transaction identifier, used in out-of-order transactions, identifies the write address group.
m_axi_usr_awlen[7:0] Output AXI4 extended burst length supports INCR burst types for 1 to 256 transfers.
m_axi_usr_awsize[2:0] Output Number of bytes per transfer, related to WDATA width.
m_axi_usr_wready Input Write data interface ready signal.
m_axi_usr_wvalid Output Write data valid signal:
1: Valid.
0: Invalid.
m_axi_usr_wdata
[AXI_DATA_WIDTH -1:0]
 Output Data signal line, transmits data information.
m_axi_usr_wstrb
[AXI_DATA_WIDTH/8-1:0]
 Output Data bus valid byte control.
For example, for a 32-bit bus, WSTRB = 4'b0010 means data in WDATA[15:8] is valid.
If all 32 bits of WDATA are valid, WSTRB should be 4'b1111.
m_axi_usr_wlast Output Asserted high when the last valid data in a write burst transfer is transmitted.
m_axi_usr_bready Output Write response interface ready signal.
m_axi_usr_bvalid Input Write response interface valid signal:
1: Valid.
0: Invalid.
m_axi_usr_bresp[1:0] Input Write response status:
0: OKEY (normal access successful).
1: EXOKEY.
2: SLVERR (slave error).
3: DECERR (decode error, e.g., no slave address).
m_axi_usr_bid[7:0] Input Transaction identifier.
m_axi_usr_arready Input Read address interface ready signal.
m_axi_usr_arvalid Output Read address interface valid signal:
1: Valid.
0: Invalid.
m_axi_usr_araddr[63:0] Output Address signal line, transmits address information.
m_axi_usr_arid[7:0] Output Transaction identifier.
m_axi_usr_arlen[7:0] Output Burst read length, AXI4 extended burst length supports INCR burst types for 1 to 256 transfers.
m_axi_usr_arsize[2:0] Output Number of bytes per transfer in a read burst.
m_axi_usr_rready Output Read data interface ready signal.
m_axi_usr_rvalid Input Read data valid signal:
1: Valid.
0: Invalid.
m_axi_usr_rid[7:0] Input Transaction identifier.
m_axi_usr_rdata
[AXI_DATA_WIDTH -1:0]
 Input Data signal line, transmits data information.
m_axi_usr_rresp[1:0] Input Read response, indicates the status of the read transfer.
m_axi_usr_rlast Input Asserted high when the last valid data in a read burst transfer is transmitted.
m_apb_usr Bus
m_apb_usr_pready Input Ready signal used by the slave to extend the APB data transfer cycle. Active high.
m_apb_usr_psel Output Transfer selection signal from master to slave. Active high.
m_apb_usr_pwrite Output Read/write indication signal. High for write, low for read.
m_apb_usr_penable Output Enable signal indicating the second and subsequent cycles of an APB transfer. Active high.
m_apb_usr_paddr[31:0] Output Address bus, up to 32 bits.
m_apb_usr_pwdata[31:0] Output Write data bus, up to 32 bits.
m_apb_usr_prdata[31:0] Input Read data bus, up to 32 bits.
m_apb_usr_pslverror Input Transfer failure indication signal returned by the slave. Optional. Active high.
AXI4-Stream Bus
CTH
s_axis_usr_tready Output Asserted high to indicate the SGDMA side is ready to receive data.
When both tready and tvalid are high, data is transferred.
When tvalid is high but tready is low, the user side must hold the valid data until tready goes high.
s_axis_usr_tvalid Input Asserted high by the user side to indicate that tdata is valid.
s_axis_usr_tlast Input Asserted high by the logic side to indicate the last data in a burst transfer.
s_axis_usr_tdata
[AXI_DATA_WIDTH -1:0]
 Input Transfer data bus. Bit width is defined by the AXI_DATA_WIDTH parameter.
s_axis_usr_tkeep
[AXI_DATA_WIDTH/8-1:0]
 Input Byte-valid indicator for the last data word in a packet.
Each bit corresponds to one byte:
1: Valid.
0: Invalid.
HTC
m_axis_usr_tready Input Asserted high to indicate the user side is ready to receive data.
When both tready and tvalid are high, data is transferred.
When tvalid is high but tready is low, the SGDMA side must hold the valid data until tready goes high.
m_axis_usr_tvalid Output Asserted high by the SGDMA to indicate that tdata is valid.
m_axis_usr_tlast Output Asserted high to indicate the last data in a burst transfer.
m_axis_usr_tdata
[AXI_DATA_WIDTH -1:0]
 Output Transfer data bus. Bit width is defined by the AXI_DATA_WIDTH parameter.
m_axis_usr_tkeep
[AXI_DATA_WIDTH/8 -1:0]
 Output Byte-valid indicator for the last data word in a packet.
Each bit corresponds to one byte:
1: Valid.
0: Invalid.
m_apb_pcie Bus
m_apb_pcie_pready Input Ready signal used by the slave to extend the APB data transfer cycle. Active high.
m_apb_pcie_psel Output Transfer selection signal from master to slave. Active high.
m_apb_pcie_pwrite Output Read/write indication signal. High for write, low for read.
m_apb_pcie_penable Output Enable signal indicating the second and subsequent cycles of an APB transfer. Active high.
m_apb_pcie_paddr[23:0] Output Address bus, up to 24 bits.
m_apb_pcie_pwdata[31:0] Output Write data bus, up to 32 bits.
m_apb_pcie_pwdata_par[3:0] Output End-to-end parity bits for m_apb_pcie_pwdata.
m_apb_pcie_pstrb[3:0] Output Write strobe signals for sparse data transfer on the write data bus.
m_apb_pcie_pstrb_par Output End-to-end parity bits for m_apb_pcie_pstrb.
m_apb_pcie_prdata[31:0] Input Read data bus, up to 32 bits.
m_apb_pcie_prdata _par[3:0] Input End-to-end parity bits for m_apb_pcie_prdata.
m_apb_pcie_pslverror Input Transfer failure indication signal returned by the slave. Optional. Active high.
s_apb_usr Bus
s_apb_usr_pready Output Ready signal used by the slave to extend the APB data transfer cycle. Active high.
s_apb_usr_psel Input Transfer selection signal from master to slave. Active high.
s_apb_ usr_pwrite Input Read/write indication signal. High for write, low for read.
s_apb_usr_penable Input Enable signal indicating the second and subsequent cycles of an APB transfer. Active high.
s_apb_usr_paddr[31:0] Input Address bus, up to 32 bits.
s_apb_usr_pwdata[31:0] Input Write data bus, up to 32 bits.
s_apb_usr_prdata[31:0] Output Read data bus, up to 32 bits.
s_apb_usr_pslverror Output Transfer failure indication signal returned by the slave. Optional. Active high.
m_byp_axi4 Bus
m_axi_byp_awready Input Write address interface ready signal.
m_axi_byp_awvalid Output Write address interface valid signal:
1: Valid.
0: Invalid.
m_axi_byp_awaddr
[AXI_ADDR_WIDTH -1:0]
 Output Address signal line, transmits address information, gives the first address of a burst transaction.
m_axi_byp_awid
[AXI_ID_WIDTH -1:0]
 Output Transaction identifier, used in out-of-order transactions, identifies the write address group.
m_axi_byp_awlen[7:0] Output AXI4 extended burst length supports INCR burst types for 1 to 256 transfers.
m_axi_byp_awsize[2:0] Output Number of bytes per transfer, related to WDATA width.
For example, if WDATA is 32-bit, AWSIZE = log2(32/8) = 2.
m_axi_byp_wready Input Write data interface ready signal.
m_axi_byp_wvalid Output Write data valid signal:
1: Valid.
0: Invalid.
m_axi_byp_wdata
[AXI_DATA_WIDTH -1:0]
 Output Data signal line, transmits data information.
m_axi_byp_wstrb
[AXI_DATA_WIDTH/8 -1:0]
 Output Data bus valid byte control.
For a 32-bit bus, WSTRB = 4'b0010 means data in WDATA[15:8] is valid.
If all 32 bits of WDATA are valid, WSTRB should be 4'b1111.
m_axi_byp_wlast Output Asserted high to indicate the last data in a burst transaction.
m_axi_byp_bready Output Write response interface ready signal.
m_axi_byp_bvalid Input Write response interface valid signal:
1: Valid.
0: Invalid.
m_axi_byp_bresp[1:0] Input Write response status:
0: OKEY (normal access successful).
1: EXOKEY.
2: SLVERR (slave error).
3: DECERR (decode error, e.g., no slave address).
m_axi_byp_bid
[AXI_ID_WIDTH -1:0]
 Input Transaction identifier.
m_axi_byp_arready Input Read address interface ready signal.
m_axi_byp_arvalid Output Read address interface valid signal:
1: Valid.
0: Invalid.
m_axi_byp_araddr
[AXI_ADDR_WIDTH -1:0]
 Output Address signal line, transmits address information.
m_axi_byp_arid
[AXI_ID_WIDTH -1:0]
 Output Transaction identifier.
m_axi_byp_arlen[7:0] Output Burst read length, AXI4 extended burst length supports INCR burst types for 1 to 256 transfers.
m_axi_byp_arsize[2:0] Output Number of bytes per transfer, related to RDATA width.
For example, if RDATA is 32-bit, ARSIZE = log2(32/8) = 2.
m_axi_byp_rready Output Read data ready signal.
m_axi_byp_rvalid Input Read data interface valid signal:
1: Valid.
0: Invalid.
m_axi_byp_rid
[AXI_ID_WIDTH -1:0]
 Input Transaction identifier.
m_axi_byp_rdata
[AXI_DATA_WIDTH -1:0]
 Input Data signal line, transmits data information.
m_axi_byp_rresp[1:0] Input Read response, indicates the status of the read transfer.
m_axi_byp_rlast Input Asserted high when the last valid data in a read burst transfer is transmitted.
SGDMA Engine Status Indicators and Interrupt Signals
Status Indicators
cfg_max_payload_size[2:0] Input MPS (Max Payload Size) indicator from PCIe IP.
3'b000: 128 bytes.
3'b001: 256 bytes.
3'b010: 512 bytes.
Others: Reserved.
cfg_max_read_req_size[2:0] Input MRRS (Max Read Request Size) indicator from PCIe IP.
3'b000: 128 bytes.
3'b001: 256 bytes.
3'b010: 512 bytes.
3'b011: 1024 bytes.
3'b100: 2048 bytes.
3'b101: 4096 bytes.
Others: Reserved.
HTC_STS[8*CHN_NUM-1:0] Output Working status of the HTC engine.
Bit[7:4]: Reserved
Bit[3]: Run
Bit[2]: Interrupt
Bit[1]: DSC done
Bit[0]: Busy
CTH_STS[8*CHN_NUM-1:0] Output Working status of the CTH engine.
Bit[7:4]: Reserved
Bit[3]: Run
Bit[2]: Interrupt
Bit[1]: DSC done
Bit[0]: Busy
Interrupt Signals
cfg_msi_enable Input MSI interrupt enable signal.
0: Disabled.
Other values: Enabled.
cfg_msix_enable Input MSI-X interrupt enable signal.
0: Disabled.
Other values: Enabled.
legacy_irq[3:0] Output Legacy interrupt request signal. Held high until acknowledged and cleared.
Bit[0]: INTA interrupt request
Bit[1]: INTB interrupt request
Bit[2]: INTC interrupt request
Bit[3]: INTD interrupt request
legacy_irq_ack Input Legacy interrupt acknowledge signal.
usr_irq
[NUM_USR_IRQ-1:0]
 Input User interrupt request signals. Held high until acknowledged and cleared.
usr_irq_ack
[NUM_USR_IRQ-1:0]
 Output User interrupt acknowledge signal. This only means that an interrupt request has been received. If the configuration is wrong, the interrupt request may fail to be sent.