user_en (0x202C)
| Bit(s) | Default | Access | Description |
|---|---|---|---|
| [USER_INTERRUPT_NUM:0] | 'h0 | RW | user_int_enmask User interrupt enable
mask 0: Interrupt generation is blocked when the user interrupt source is
asserted. 1: An interrupt is generated on the rising edge of the user
interrupt source. If both the “Enable Mask” and the source are set, a user interrupt
is generated. |