MSI-X/MSI Interrupt Vector Table (0x8000)

The SGDMA IP supports MSI-X and MSI interrupts. The interrupt vector table supports up to 32 interrupt vectors. The table starts at address 0x8000, and the Pending Bit Array (PBA) is located at address 0x8FE0. The MSI interrupt address is the pcie_dma0_control bar address of the DMA. Details are as follows.

Table 1. Interrupt Vector Table
Byte Offset Bits Default Access Description
0×00 [31:0] 32’h0 RW Lower 32 bits of the address for MSI-X interrupt vector 0.
0×04 [31:0] 32’h0 RW Upper 32 bits of the address for MSI-X interrupt vector 0.
0×08 [31:0] 32’h0 RW Data field for MSI-X interrupt vector 0.
0×0C [31:0] 32’hFFFFFFFF RW Control field for MSI-X interrupt vector 0.
  • Bits [31:1]: Reserved.
  • Bit [0]: Mask bit for the MSI-X interrupt vector. When set to 1, the interrupt message is suppressed; when cleared to 0, the interrupt message is allowed.
... – – – –
0×1F0 [31:0] 32’h0 RW Lower 32 bits of the address for MSI-X interrupt vector 31.
0×1F4 [31:0] 32’h0 RW Upper 32 bits of the address for MSI-X interrupt vector 31.
0×1F8 [31:0] 32’h0 RW Data field for MSI-X interrupt vector 31.
0×1FC [31:0] 32’hFFFFFFFF RW Control field for MSI-X interrupt vector 31.
  • Bits [31:1]: Reserved.
  • Bit [0]: Mask bit for the MSI-X interrupt vector. When set to 1, the interrupt message is suppressed; when cleared to 0, the interrupt message is allowed.
0×FE0 [31:0] 32’h0 RW Pending Bit Array (PBA). Each bit corresponds to an interrupt vector.
0×F00 [31:0] 32’h0 RW Lower 32 bits of the address for MSI interrupt.
0×F04 [31:0] 32’h0 RW Upper 32 bits of the address for MSI interrupt.
0×F08 [31:0] 32’h0 RW Data field for MSI interrupt.