Resource Utilization and Performance

These resource and performance values are based on specific supported FPGAs. These values serve as a guideline only and may vary depending on device resource utilization, design congestion, and user design modifications.

Table 1. Titanium Resource Utilization and Performance
FPGA Model	Configuration		Timing Model	Logic Element (XLR)	Memory Blocks	DSP Blocks	f_MAX (MHz)	Efinity® Version
FPGA Model	HTC & CTH Channel	User Interface	Timing Model	Logic Element (XLR)	Memory Blocks	DSP Blocks	f_MAX (MHz)	Efinity® Version
Ti375N1156	1	AXIMM	C4	24,745	47	0	264	2025.2
	4	AXIMM		89,418	52	0	270
	1	AXIST		45,527	66	0	272
	4	AXIST		109,675	108	0	257