htc_dma_status (0x3028)
| Bit(s) | Default | Access | Description |
|---|---|---|---|
| 31:24 | – | – | Reserved |
| 23:19 | – | – | Reserved |
| 18:14 | – | – | Reserved |
| 13:9 | – | – | Reserved |
| 8:7 | – | – | Reserved |
| 6 | 1'b0 | RW | Descriptor Completed flag status field. This field is cleared when the
run bit [0] of the control register transitions from 0 to 1. When the
corresponding logging enable bit in the control register is set to 1, this bit is
asserted high by the HTC engine after completing the data transfer of a descriptor
with the Completed flag. |
| 5 | 1'b0 | RW | Descriptor Stop flag status field. This field is cleared when the run bit
[0] of the control register transitions from 0 to 1. When the
corresponding logging enable bit in the control register is set to 1, this bit is
asserted high by the HTC engine after completing the data transfer of a descriptor
with the Stop flag. |
| 4 | – | – | Reserved |
| 3 | – | – | Reserved |
| 2 | – | – | Reserved |
| 1 | – | – | Reserved |
| 0 | 1'b0 | RO | HTC engine Busy status. This bit is set to 1 when the HTC engine is
performing data transfer, and cleared to 0 when the engine is idle. |