| 31:28 |
– |
– |
Reserved |
| 27:23 |
– |
– |
Reserved |
| 22:18 |
– |
– |
Reserved |
| 17:13 |
– |
– |
Reserved |
| 12 |
– |
– |
Reserved |
| 11 |
1'b0 |
RW |
When the CTH engine’s user-side interface is set to AXI4-Stream mode, setting
this bit to 1 disables CTH writeback information and enables the default writeback
behavior. |
| 10 |
0x0 |
RW |
Writeback enable bit for polling mode. When set to 1, after the CTH engine
completes data transfer for descriptors with the Completed flag, the writeback engine
writes the number of completed descriptors to a preconfigured memory address for the
host to check transfer completion. |
| 9:7 |
– |
– |
Reserved |
| 6 |
1'b0 |
RW |
When set to 1, enables logging of descriptors with the Completed flag in the
Status register. If the corresponding interrupt enable bit is 1, an interrupt is
generated. |
| 5 |
1'b0 |
RW |
When set to 1, enables logging of descriptors with the Stop flag in the
Status register. If the corresponding interrupt enable bit is 1, an interrupt is
generated. |
| 4 |
– |
– |
Reserved |
| 3 |
– |
– |
Reserved |
| 2 |
– |
– |
Reserved |
| 1 |
– |
– |
Reserved |
| 0 |
1'b0 |
RW |
CTH engine run enable bit. When set to 1, the CTH engine starts data
transfer. When cleared to 0, the transfer is stopped. If the engine is busy when
cleared, it finishes the current descriptor before stopping. |