dma_irq_i (0x2010)
| Bit(s) | Default | Access | Description |
|---|---|---|---|
| [31:NUM_ENGINE] | – | – | Reserved |
| [NUM_ENGINE-1:0] | ’h0 | RO | Interrupt pending status for each engine. Each bit corresponds to a read
or write engine. This register indicates that a pending interrupt condition
exists. The pending status can be cleared by removing the cause of the
interrupt condition at the source component. The bits for HTC (Host to
Card) engines always start from bit 0. The bits for CTH (Card to Host)
engines follow the last HTC bit. |