| 31:24 |
– |
– |
Reserved |
| 23:19 |
– |
– |
Reserved |
| 18:14 |
– |
– |
Reserved |
| 13:9 |
– |
– |
Reserved |
| 8:7 |
– |
– |
Reserved |
| 6 |
1'b0 |
RW |
Interrupt enable bit corresponding to the status field for descriptors with
the Completed flag. When set to 1, an interrupt is generated simultaneously as the
status is logged in the Status register. |
| 5 |
1'b0 |
RW |
Interrupt enable bit corresponding to the status field for descriptors with
the Stop flag. When set to 1, an interrupt is generated simultaneously as the status
is logged in the Status register. |
| 4 |
– |
– |
Reserved |
| 3 |
– |
– |
Reserved |
| 2 |
– |
– |
Reserved |
| 1 |
– |
– |
Reserved |
| 0 |
– |
– |
Reserved |