| [31:NUM_ENGINE] |
— |
— |
Reserved |
| [NUM_ENGINE-1:0] |
’h0 |
RO |
SGDMA interrupt request status for HTC and CTH engines. NUM_ENGINE represents
the total number of HTC and CTH engines. Each bit corresponds to the interrupt request
of one engine. A bit is asserted only when both the interrupt source and its
corresponding interrupt enable bit are active. The mapping of each bit to the
respective engine is illustrated in the reference diagram. HTC engines are mapped
starting from bit [0], followed by CTH engines. |