APB3 Configuration Interface

The IP provides register configuration through two sets of APB3 interfaces:
  • M_APB3
  • S_APB3

The M_APB3 interface provides user-side register access. The host initiates read and write requests to this interface through PCIe, which is mapped to the BAR0/1 space.

The S_APB3 interface is dedicated to managing internal SGDMA registers and is restricted to internal operations within the user logic. It does not provide access to PCIe registers and does not initiate requests to the host.