reg_write_timeout (0x000C)
| Bit(s) | Default | Access | Description |
|---|---|---|---|
| 4:0 | 5’h0 | RW | Write flush timeout. Applies to the AXI4-Stream CTH channel. This
register specifies the number of clock cycles the channel waits for data before
flushing received write data from PCIe. This operation closes the descriptor and
triggers a writeback. A value of 0 disables the timeout. Timeout
period = 2value clock cycles. |