dma_en (0x2038)
| Bit(s) | Default | Access | Description |
|---|---|---|---|
| [DMA_INTERRUPT_NUM:0] | – | RW | channel_int_enmask SGDMA interrupt enable mask. Each read/write engine is
mapped to one bit. 0: Interrupt generation is blocked when the
interrupt source is asserted. HTC bits always start from bit 0. CTH bits are placed
after the last HTC bit, depending on the HTC_CH_NUM
parameter.1: An interrupt is generated on the rising edge of the
interrupt source. If both the enmask bit and the source are asserted, an interrupt
is generated. |