htc_dma_ctl (0x301C)

Table 1. htc _dma_ctl (0x301C)
Bit(s) Default Access Description
31:28 Reserved
27:23 Reserved
22:18 Reserved
17:13 Reserved
12 Reserved
11 1'b0 RW In AXI4-Stream mode, disables HTC write-back and enables default write-back when set to 1.
10 0x0 RW Polling mode enable. When set to 1, the HTC engine automatically writes back the completion count to a predefined memory address after processing descriptors with the Completed flag, for host polling.
9:7 Reserved
6 1'b0 RW Enables logging of descriptor completion flags in the Status register. If the corresponding interrupt enable bit is asserted, an interrupt is triggered simultaneously.
5 1'b0 RW Enables logging of descriptor stop flags in the Status register. If the corresponding interrupt enable bit is asserted, an interrupt is triggered simultaneously.
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 1'b0 RW Run bit for the HTC engine. When set to 1, the engine starts data transfer. Clearing this bit stops the engine after completing the current descriptor if busy.