Register List

Table 1. Register List
Base Address Channel Offset Dword Offset Name R/W Description
0x00000000 0x00 cfg_identifier RO Configuration identifier
0x04 reg_user_max_payload RO User-defined maximum payload register
0x08 reg_user_max_read_req RO User-defined maximum read request register
0x0C reg_write_timeout RO Write timeout register
0x18 msi_enable&msix_enable RO MSI/MSI-X interrupt enable
0x1C max_payload RO Maximum payload register
0x20 max_read_req RO Maximum read request register
0x24 clk_pciew RO PCIe width: (0, 1, 2, 3) represent (64, 128, 256, 512)
0x00001000 0x00 dsc_identifier RO Descriptor identifier
0x04 dsc_crd_en RW Enable signal for HTC/CTH channel credit
0x0C dsc_stop Descriptor fetch stop signal for the corresponding channel
0x18 dsc_restart RW Reset signal for HTC/CTH channel credit
0x00002000 0x00 irq_identifier RO Interrupt identifier
0x04 user_irq RO User interrupt request indicator
0x08 dma_irq RO SGDMA interrupt request indicator
0x0C user_irq_i RO User interrupt pending indicator
0x10 dma_irq_i RO SGDMA interrupt pending indicator
0x14 user_irq_lut RW User interrupt vector lookup
0x18 user_irq_lut RW User interrupt vector lookup
0x1C user_irq_lut RW User interrupt vector lookup
0x20 user_irq_lut RW User interrupt vector lookup
0x24 dma_irq_lut RW SGDMA interrupt vector lookup
0x28 dma_irq_lut RW SGDMA interrupt vector lookup
0x2C user_en RW User interrupt enable register
0x38 dma_en RW SGDMA interrupt enable register
0x00003000 0x000
/
0x100
/
0x200
/
0x300		 0x00 htc_identifier RO HTC identifier
0x04 htc_dsc_adj RW Number of adjacent descriptors for HTC
0x08 htc_dsc_crd RW HTC channel credit value
0x0C htc_dsc_addr_l RW HTC descriptor lower base address
0x10 htc_dsc_addr_h RW HTC descriptor upper base address
0x14 htc _dma_wb_addr_l RW HTC descriptor writeback lower address
0x18 htc _dma_wb_addr_h RW HTC descriptor writeback upper address
0x1C htc _dma_ctl RW HTC engine control register
0x28 htc _dma_status RO HTC engine status register
0x30 htc _dma_dsc_compl_cnt RO HTC engine SGDMA completed descriptor count register
0x38 htc _dma_intr_mask RW HTC engine SGDMA interrupt enable register
0x00004000 0x000
/
0x100
/
0x200
/
0x300		 0x00 cth_identifier RO CTH identifier
0x04 cth_dsc_adj RW Number of adjacent descriptors for CTH
0x08 cth_dsc_crd RW CTH channel credit value
0x0C cth_dsc_addr_l RW CTH descriptor lower base address
0x10 cth_dsc_addr_h RW CTH descriptor upper base address
0x14 cth _dma_wb_addr_l RW CTH descriptor writeback lower address
0x18 cth _dma_wb_addr_h RW CTH descriptor writeback upper address
0x1C cth _dma_ctl RW CTH engine control register
0x28 cth _dma_status RW CTH engine status register
0x30 cth _dma_dsc_compl_cnt RW CTH engine SGDMA completed descriptor count register
0x38 cth _dma_intr_mask RW CTH engine SGDMA interrupt enable register
0x00008000 0x00 Interrupt vector table RW MSI and MSIX interrupt vector table
0x80000000 Bypass DMA register space. Use this base address space with 24-bit APB address to access the transceiver hard block APB register.