Features
PCIe Scatter-Gather Direct Memory Access
supports:
- Data transfer using the standard AXI4-MM protocol
- Data transfer in AXI4-Stream mode
- Master APB3 interface for host-to-card register configuration
- Slave APB3 interface for user logic-to-IP register configuration
- Legacy and MSI-X interrupts
The following table provides for a more indepth overview of the features supported by the
PCIe SGDMA IP core.
| Feature | Efinix PCIe SGDMA IP |
|
|---|---|---|
| Data width |  256 bits |
|
| Host-to-Card | Up to four channels | |
| Card-to-Host | Up to four channels | |
| Descriptor Engine Pause Control | Supported |
|
| AXI-MM Bypass Interface | Supported |
|
| Descriptor | Up to 256 MB data
length per descriptor |
|
| Write back/polling | Supported | |
| Legacy INTX | Single channel (INTA
only) |
|
| User INTR | INTA
MSIX MSI |
|
| MSIX | Supported |
|
| MSI | Supported |
|
| MPS, MRRS | MPS = 128, 256,
512 MRRS = 128, 256, 512, 1024, 2048,
4096 Measured in bytes |
|
| Clock frequency | AXI clock = {125 to
250} MHz APB clock = {20 to 200} MHz Must use same CLK
source as PCIe EP |
|
| APB interface | Supported | |
| AXI4-MM interface | Supported | |
| AXI4-Stream interface | Supported | |