Descriptors

A descriptor is the basic control unit for SGDMA transfer, used to define the attributes and control information for a single data transfer. Its structure is as follows:

Figure 1. Descriptor Structure
  • Descriptor: 32 bytes, defines the source address, destination address, and length for a single transfer. The descriptor must be 32-byte aligned in memory.
  • Descriptor Block: Composed of multiple consecutive descriptors. The descriptors within the same block are stored consecutively in memory and cannot span a 4 KB memory boundary.
  • Descriptor List: Composed of multiple descriptor blocks defining a complete SGDMA transfer task. The descriptor blocks are linked together using a linked list, and they do not need to be stored consecutively in memory.
Table 1. Descriptor Format Table
Offset Field Description
0x0 des_header_h [4:0]: Upper 5 bits of the data transfer length.
[31:5]: Reserved, default value is 0.
0x04 des_header_l [0]: Completed bit, set to 1 to indicate that an interrupt should be generated after the data transfer is complete.
[1]: Stop bit, set to 1 to indicate that the SGDMA engine should stop requesting new descriptors.
[2]: EOP bit, end-of-packet flag for AXI4-Stream interface.
[8:3]: nxt_adj, represents the remaining number of descriptors in the current block.
[31:9]: Lower 23 bits of the data transfer length, combined with des_header_h [4:0] to form a 28-bit data length, in bytes.
0x08 src_addr_h Upper 32 bits of the source address for data transfer.
0x0C src_addr_l Lower 32 bits of the source address for data transfer.
0x10 dst_addr_h Upper 32 bits of the destination address for data transfer.
0x14 dst_addr_l Lower 32 bits of the destination address for data transfer.
0x18 des_link_address_h Upper 32 bits of the next descriptor address.
0x1C des_link_address_l Lower 32 bits of the next descriptor address.
The operational flow of the descriptor is as follows:
  1. List Creation: The host driver creates the descriptor list and stores it in the host memory.
  2. Register Configuration: The host driver configures the SGDMA registers through the BAR space and initializes the following parameters:
    • Start address of the current descriptor list (HTC: 0x300C and 0x3010; CTH: 0x400C and 0x4010).
    • Number of descriptors in the first descriptor block of the current descriptor list (HTC: 0x3004; CTH: 0x4004).
  3. Transfer Start: The SGDMA engine fetches descriptors from the starting address of the current descriptor list and uses the des_link_address field of the descriptor to obtain the address of the next descriptor.
  4. Descriptor Block Processing:
    • Descriptors within the same descriptor block have consecutive addresses and the next descriptor address can be obtained by offsetting 32 bytes from the current descriptor address.
    • When the nxt_adj value of a descriptor is 0, it indicates that the current descriptor is the last descriptor in the descriptor block. The next descriptor block address is obtained via the des_link_address field.
  5. List Termination: When the stop bit of a descriptor is set to 1, it indicates that the current descriptor list has ended. The SGDMA engine will stop the transfer task after completing this descriptor.