Functional Description

This section outlines some of the capabilities of the PCIe SGDMA IP core.

Figure 1. SGDMA Block Diagram
The SGDMA IP enables data transfer between the host memory and user logic via the PCIe interface. It supports two transfer modes:
  • Host-to-Card (HTC)
  • Card-to-Host (CTH)

Both modes support bidirectional data transfer between the and the host. Using a chained descriptor queue mechanism, the SGDMA engine efficiently and flexibly handles data transfer tasks.

The operational flow for SGDMA is as follows:
  1. Descriptor Configuration: The driver on the host side configures software descriptors and builds the transfer queue.
  2. Data Transfer: The SGDMA engine actively reads the descriptor commands from the queue and performs the data transfer operations.
  3. Full-Duplex Processing: The SGDMA engine supports multitasking with parallel processing. The HTC and CTH engines operate independently to handle data transfers from host to and from to host, respectively.

On the user logic side, the SGDMA provides either an AXI4 memory-mapped (AXI4-MM) master interface or an AXI4-Stream interface for integration with user logic. On the PCIe controller side, it connects via an AXI4-MM master interface. The SGDMA performs data transfers based on descriptors, which contain information such as source address, destination address, data length, and the address of the next descriptor in a chain. The SGDMA fetches and parses descriptors from host memory, and upon completing the transfer, it notifies the host of the transfer status via interrupt.

In addition, this IP integrates an SGDMA bypass mode that allows the host to access device memory directly for read/write operations without going through the SGDMA engine. This is suitable for low-latency applications involving small data volumes. Working with the SGDMA transfer engine, it provides a flexible data access solution for the system.