Reset Signals

During the FPGA power-up, all three reset signals must be initialized to 0 to reset the entire Ethernet 10G MAC core to its initial known state.

The init_clk signal needs to be sourced and free-running. When the FPGA is in user mode, you need to deassert init_rst_n to kick-start the power-up sequence with the FPGA PHY. The init_rst_n signal is to remain deasserted throughout the operation. Details of the power-up sequence are being described in Power Up Handshake with FPGA Transceiver.

When mac_reset_n is asserted, it resets the core logic of the Ethernet 10G MAC core, including TX and RX, and statistic reporting. The power-up sequence module remains intact and operational.

When cnt_rst_n is asserted, it resets all the statistic reporting in TX and RX. Except for the statistic counters, the logic of the Ethernet 10G MAC core remains operational. The power-up sequence module remains intact.

These 3 reset signals are asynchronous, but the deassertion of each reset signals is synchronous. For init_rst_n, there is an internal reset synchronizer to align the deassertion of init_rst_n to init_clk. For mac_reset_n and cnt_rst_n, there is a respective internal reset synchronizer to synchronize the deassertion of mac_reset_n and cnt_rst_n to mac10gbe_clk.

Each reset synchronizer has a latency of 2 to 3 clock cycles.

The Figure 1 shows the reset domains in the Ethernet 10G MAC core.