Latency

In the 2025.1 release and later, the latency of the Ethernet 10G MAC core has been improved. During Cut Through mode, the TX frame transmission has a new latency of 3 clock cycles, while the RX frame transmission has a new latency of 5 or 6 clock cycles.

At the RX path, there is a new configuration named Optimize Timing. The default setting for this configuration is Enable. When set to Enable, the 1^st level of pipeline registers is synthesized to improve timing closure, and the total latency in the RX path is 6 clock cycles. Alternatively, depending on the complexity of your design and the timing report, you can set this configuration to Disable. When set to Disable, there will be no pipeline registers being synthesized, and the total latency in the RX path is reduced to 5.