Non-Compliant TX_AXI_TLAST
An Ethernet frame should consist minimally destination address, source address, optional
VLAN tag and ETHERTYPE/LEN. This means that an Ethernet frame spans across a minimum of
2 clock cycles, where TX_AXI_TLAST should be pulse based.
Figure 1
illustrates a case of non-compliant
TX_AXI_TLAST.- At label (3c), the Ethernet frame spans only 1 clock cycle. Here,
TX_AXI_TLASTis asserted at the start of the frame, resulting in a silent drop of the ≤ 8 octets of the short frame with incomplete headers. - At labels (3a) and (3b),
TX_AXI_TLASTspans multi-clock cycles, Ethernet 10G MAC core decodes it as 2 invalid short frames and silently drops the 2 frames of ≤ 8 octets.
Note: There is no indicator on the silently dropped TX frame. In
replacement of the silently dropped TX Frame, XGMII TX transmits IDLE.
TX_AXI_TLAST