Clock Sources

The Ethernet 10G MAC core has 2 independent clock sources:
  • init_clk
  • mac10gbe_clk
Table 1. Ethernet 10G MAC Core Clock Sources
Clock Name Frequency Description
INIT_CLK ≤ 50 MHz To facilitate the power-up sequence of the FPGA transceiver PHY.
Can be sourced from the PLL or CLKIN pin.
MAC10GBE_CLK 156.25 MHz Sourced from the FPGA transceiver forwarded clock to be the source synchronous.
Eliminates additional clock PPM.
The forwarded clock is used to clock the 10G PCS in the FPGA transceiver.

The Figure 1 shows the clock domains in the Ethernet 10G MAC core.

Figure 1. Ethernet 10G MAC Core Clock Domain