Example Design Macros

The example design includes useful macros that allow you to customize and enable the KR Training and Auto Negotiation (Clause 37) in the FPGA 10G PCS. Using the macros, you can plug in the example design into the Functional Verification Testbench to perform extensive functional verification. By default, macros are disabled.

The following are the available macros in the example design:
  • KR ENABLE
    • Enable KR Training in the FPGA 10G PCS.
    • Pre-requisite: Enable KR Training in the Interface Designer.
    • Ineffective when the LOOPBACK macro is enabled.
  • AN ENABLE
    • Enable Auto Negotiation (Clause 37) in the FPGA 10G PCS.
    • Pre-requisite: Enable Auto Negotiation (Clause 37) in the Interface Designer.
    • Ineffective when the LOOPBACK macro is enabled.
  • LOOPBACK
    • Redirect the XGMII TX to the XGMII RX. Available for Q1_L0 instance only.
    • When enabling this LOOPBACK macro, the Ethernet 10G MAC core is segregated from the FPGA 10G PCS. Hence, the PCS features are not available, resulting in KR_ENABLE and AN_ENABLE becoming ineffective.
  • VERIF
    • This macro provides the flexibility to migrate and plug in the example design into the Functional Verification Testbench.
    • When this macro is enabled, you may use the driver in the Functional Verification Testbench to inject vectors into the Ethernet 10G MAC core. Simultaneously, you may use the scoreboard in the Functional Verification Testbench to check and verify the output from the Ethernet 10G MAC core.
    • The Virtual I/O Debugger is disconnected when this macro is enabled.
    • When this macro is not enabled, you can use the Virtual I/O Debugger to drive the input vectors into the Ethernet 10G MAC core.