Ports

Table 1. Ethernet 10G MAC Core Ports Interface
Port Name Direction Bus Width Clock Domain Description
Clock and Reset1
init_clk2 Input 1 – Frequency = 50 MHz or below
init_rst_n2 Input 1 Async Reset all power-up handshake between the core and the FPGA PHY.
mac10gbe_clk Input 1 – Frequency = 156.25 MHz
mac_reset_n Input 1 Async Reset all the core logic of the Ethernet 10G MAC core, which includes statistics reporting.
cnt_rst_n Input 1 Async Assert this port to reset all statistics reporting.
MAC AXI ST Interface: TX
tx_axis_mac_tdata Input 64 mac10gbe_clk AXI ST 64 TX Interface. Refer to TX AXI ST 64.
tx_axis_mac_tvalid Input 1 mac10gbe_clk
tx_axis_mac_tlast Input 1 mac10gbe_clk
tx_axis_mac_tkeep Input 8 mac10gbe_clk
tx_axis_mac_tuser Input 1 mac10gbe_clk
tx_axis_mac_tready Output 1 mac10gbe_clk
MAC AXI ST Interface: RX
rx_axis_mac_tdata Output 64 mac10gbe_clk AXI ST 64 RX Interface. Refer to RX AXI ST 64.
rx_axis_mac_tvalid Output 1 mac10gbe_clk
rx_axis_mac_tlast Output 1 mac10gbe_clk
rx_axis_mac_tkeep Output 8 mac10gbe_clk
rx_axis_mac_tuser Output 1 mac10gbe_clk
MAC Source Address3
mac_source_
address_port
 Input 48 Pseudo Async Drive static (or pseudo-static) values in hexadecimal to the input port to configure the MAC Source Address. Refer to Customizing the Ethernet 10G MAC.
Port Name Direction Bus Width Clock Domain Description
MAC Priority Flow Control4
rx_pause_ignore Input 1 mac10gbe_clk Assert this signal to disable the priority flow control. This is a pseudo static user's input signal.
tx_pause_gen Input 1 mac10gbe_clk Assert this to trigger TX Pause request, i.e. to send TX Pause frame to XGMII TX interface, with the quant values from tx_pause_quant. This signal is pulse based, and should only be asserted when tx_pause_busy is 0.
tx_pause_busy Output 1 mac10gbe_clk An indicator of the status of TX Pause request. When this signal is 1, this means there is TX pause request being queued, pending processed. Any assertion on tx_pause_gen or tx_pause_quant will not be processed when this signal is 1. This signal will become 0 when the TX Pause request has been processed. When this signal is 0, it also means that user can request a new TX Pause request by asserting tx_pause_gen.
tx_pause_quant Input 16 Pseudo Async Drive this bus with the desired quant value to be included during the TX Pause request. 1 quant is defined as the pause time to transfer 512 bits. Quant value should be stable before asserting tx_pause_gen.
MAC Broadcast Filtering & Address Filtering5
rx_address_
filtering_mask
 Input 48 Pseudo Async This is a bit-wise filtering mask for address filtering. Any bit, when asserted, is compared bit-wise against source address and any mismatched comparison is filtered or dropped. When any of the bit-wise mask is set to 0, the corresponding bit is considered matched.
MAC Statistic Reporting: TX6
cnt_tx_frame_
transmitted_good
 Output 32 mac10gbe_clk Reports the number of TX frames successfully transferred at XGMII Interface.
cnt_tx_frame_
pause_mac_ctrl
 Output 32 mac10gbe_clk Reports the number of TX Pause frames successfully transferred from tx_pause_gen to XGMII Interface.
cnt_tx_frame_error_
txfifo_overflow
 Output 32 mac10gbe_clk Reports the number of TX frames being scrapped due to TXFIFO overflow, during Store Forward mode. During Cut Through mode, this statistic stays 0.
cnt_tx_frame_is_fe Output 32 mac10gbe_clk Reports the number of Bad TX frames being terminated. This statistic does not include the silently dropped TX frames due to non-compliant TX_AXI_TLAST or the scrapped TX frames due to TXFIFO Overflow.
Port Name Direction Bus Width Clock Domain Description
MAC Statistic Reporting: RX7
rpt_rx_frame_length Output 15 mac10gbe_clk Reports the length of each RX frames received at RX AXI ST Interface.
cnt_rx_frame_
received_good
 Output 32 mac10gbe_clk Reports the number of Good Frames at RX AXI ST.
cnt_rx_frame_
received_total
 Output 32 mac10gbe_clk Reports the number of all frames at RX, i.e. good frames, bad frames, and pause frames. This statistic includes dropped frames.
cnt_rx_frame_errors Output 32 mac10gbe_clk Reports the number bad frames and dropped frames at RX.
cnt_rx_frame_
pause_mac_ctrl
 Output 32 mac10gbe_clk Reports the number of pause frames at RX.
cnt_rx_frame_
error_fcs
 Output 32 mac10gbe_clk Reports the number of RX frames containing CRC error.
cnt_rx_frame_
undersized
 Output 32 mac10gbe_clk Reports the number of short RX frames. Short RX frames are RX frames with a payload size < 46 or VLAN-tagged RX frames with a payload size < 42.
cnt_rx_frame_
oversized
 Output 32 mac10gbe_clk Reports the number of RX frames with physical length less than the value set in Maximum Transmission Unit Frame Length.
cnt_rx_frame_
mismatched_
length
 Output 32 mac10gbe_clk Reports the number of RX frames with physical length mismatching the ETHERTYPE/LEN field. This statistic is only applicable for RX frames with payload size ≤ 1500.
cnt_rx_frame_
filtered_by_
address
 Output 32 mac10gbe_clk Reports the number of RX frames being silently dropped due to address mismatch or RX frames with broadcast address. This statistic is subjected to the enabling of Broadcast Filtering and rx_address_filtering_mask.
XGMII Interface
XGMII_TXD Output 64 mac10gbe_clk XGMII TX Data.
XGMII_TXC Output 8 mac10gbe_clk XGMII TX Control.
XGMII_RXD Input 64 mac10gbe_clk XGMII RX Data.
XGMII_RXC Input 8 mac10gbe_clk XGMII RX Control.
Port Name Direction Bus Width Clock Domain Description
PHY Power Up Sequence8
PMA_CMN_READY Input 1 Async Output from PHY to indicate the readiness of PHY calibration.
PMA_XCVR_
PLLCLK_
EN_ACK
 Input 1 Async Refer to Power Up Handshake with FPGA Transceiver.
PMA_XCVR_
POWER_
STATE_ACK
 Input 4 Async
PMA_RX_SIGNAL_
DETECT
 input 1 Async
PMA_XCVR_
PLLCLK_EN
 Output 1 init_clk
PMA_XCVR_
POWER_
STATE_REQ
 Output 4 init_clk
phy_init_done Output 1 Async
1 For details on Clock and Reset, refer to Clock Sources and 5.3 Reset Signals.
2 The built-in power-up sequence module can be disabled by driving 0 to input ports of init_clk, init_rst_n, PMA_CMN_READY, PMA_XCVR_PLLCLK_EN_ACK, PMA_XCVR_POWER_STATE_ACK, and PMA_RX_SIGNAL_DETECT.
3 The input port mac_source_address_port is only available if Configure MAC Source Address Thru Port is set to Yes.
4 For details on MAC Priority Flow Control, refer to Priority Flow Control (Duplex Mode).
5 For details on MAC broadcast and address filtering, refer to Address Filtering and Broadcast Filtering at RX.
6 For details on MAC statistic reporting, refer to Statistic Reporting.
7 For details on MAC statistic reporting, refer to Statistic Reporting.
8 The built-in power-up sequence module can be disabled by driving 0 to input ports of init_clk, init_rst_n, PMA_CMN_READY, PMA_XCVR_PLLCLK_EN_ACK, PMA_XCVR_POWER_STATE_ACK, and PMA_RX_SIGNAL_DETECT.