Ethernet 10G MAC Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

Efinix provides the following example design that targets Titanium Ti375 N1156 Development Board.

Note: The Ethernet 10G MAC core example design is available in Efinity software version 2024.2.294.1.19 and later.

The example design demonstrates the connectivity of the Ethernet 10G MAC core, FPGA 10G PCS, and the user's logic, as shown in the Figure 1 and Figure 1. The user’s logic has 2 pattern generators and checkers (denoted by efx_mac10gbe_exp_pat_gen and efx_mac10gbe_exp_checker modules, respectively), APB modules (denoted by efx_mac10gbe_exp_apb_master and efx_mac10gbe_exp_apb_halt), and a Virtual I/O Debugger.

The example design further demonstrates the essential APB commands and handshakes to enable the RX path in the CDR-Locked-to-Data, as described in Power Up Handshake with FPGA Transceiver. The APB master has built-in ROM and RAM.

Figure 1. Example Design for Ethernet 10G MAC Core

The built-in ROM stores the configuration settings to enable the RX path and/or Auto Negotiation (Clause 37). Figure 2 describes the format of the ROM content.

Concurrently, the built-in RAM captures the APB_PRDATA and APB_PADDRESS of all APB read commands. The ram_dout_d and ram_dout_a ports display the captured APB_PRDATA and the corresponding APB_PADDRESS.

Figure 2. Format of an APB ROM Content

In user mode, the example design awaits the PLL to lock. The assertion of PLL_LOCK releases the resets in the Ethernet 10G MAC core and the FPGA PCS. This is followed by the PHY power-up sequence handshake, resulting in the assertion of PHY_INIT_DONE. Upon the assertion of PHY_INIT_DONE, the APB modules become operational and begin APB configuration based on the built-in ROM content. At the end of the APB configuration, the RX path in the FPGA becomes functional and achieves BLOCK LOCK status. Upon achieving BLOCK LOCK status, the pattern generator starts transmitting data frames into the TX AXI ST interface of the Ethernet 10G MAC core.

For the entire operation, the checker actively checks the RX path of the Ethernet 10G MAC core for error frames and assertion of RX_AXI_TUSER. Depending on the macro enablement, the checker also checks for a successful Auto Negotiation state and KR Training. Finally, the PASS_STATUS is asserted if all the passing criteria are met.