Efinity: IP Catalog, Interface Designer, and Integration

The Ethernet 10G MAC core is designed to interact with the user's logic and the FPGA Ethernet 10G PCS as shown in Figure 1. To combine the Ethernet 10G MAC core, the FPGA Ethernet 10G PCS and the user's logic together as a whole design, you need to perform the following steps:

1. Configure and generate the Ethernet 10G MAC core from the IP Catalog.
2. Configure and generate the FPGA Ethernet 10G PCS using the Interface Designer.
3. Create a top-level module to integrate the Ethernet 10G MAC core (from step 1), the FPGA Ethernet 10G PCS (from step 2) and the user's logic.