Virtual I/O Debugger Settings
This example design uses a plug-in interface called the Virtual I/O Debugger. This interface allows you to download the bitstream to your device. After the downloads are complete, you can use the Virtual I/O Debugger interface to probe and control the signals of the example design. To control the settings, refer to Virtual I/O Debugger settings.
Important: The Virtual I/O Debugger is available if the
VERIF macro is disabled.Note: In the following table, the signal names are prefixed with
q1_, q1_l0_, and q1_l1_ to
indicate and distinguish these instances. For detailed signal description, refer to Titanium Ethernet 10GBase-KR User Guide and tables
in the Virtual I/O Debugger Settings.| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| PLL_LOCKED | 1 | Probe | Lock signal from PLL, indicating that the clock sources (INIT_CLK,
Q1_APB_CLK, and DEBUG_CLK) are stable. Refer to Figure 1. This signal starts the operation of the example design,
where the assertion of PLL_LOCK releases the resets
in the Ethernet 10G MAC
core and the FPGA PCS. |
| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| Q1_PMA_CMN_READY | 1 | Probe | Refer to the signal description in the Power Up Sequence chapter of the Titanium Ethernet 10GBase-KR User Guide. |
| Q1_L0_RX_SIGNAL_DETECT | 1 | Probe | |
| Q1_L1_RX_SIGNAL_DETECT | 1 | Probe |
| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| Instance Q1 Lane 0 | Refer to the signal description in the Signals
per Lane table in the Signal chapter of the Titanium Ethernet 10GBase-KR User Guide. |
||
| Q1_L0_KR_TRAINING | 1 | Probe | |
| Q1_L0_KR_FRAME_LOCK | 1 | Probe | |
| Q1_L0_KR_LOCAL_RX_TRAINED | 1 | Probe | |
| Q1_L0_KR_SIGNAL_DETECT | 1 | Probe | |
| Q1_L0_KR_TRAINING_FAILURE | 1 | Probe | |
| Instance Q1 Lane 1 | |||
| Q1_L1_KR_TRAINING | 1 | Probe | |
| Q1_L1_KR_FRAME_LOCK | 1 | Probe | |
| Q1_L1_KR_LOCAL_RX_TRAINED | 1 | Probe | |
| Q1_L1_KR_SIGNAL_DETECT | 1 | Probe | |
| Q1_L1_KR_TRAINING_FAILURE | 1 | Probe | |
| Instance Q1 Lane 0 and Q1 Lane 1 | Refer to Base-KR Training Success and
Base-KR Training Failure figures for signal
behavior in the Base-KR Training chapter of the Titanium Ethernet 10GBase-KR User Guide.Efinix recommends that you control
this signal column by selecting Active-High
from a drop-down list in the control column. |
||
| Q1_L0_restart_kr_training_vio | 1 | Source | |
| Q1_L1_restart_kr_training_vio | 1 | Source | |
| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| Instance Q1 Lane 0 | Refer to the signal description in the Signals
per Lane table in the Signal chapter of the Titanium Ethernet 10GBase-KR User Guide. |
||
| Q1_L0_BLOCK_LOCK | 1 | Probe | |
| Q1_L0_HI_BER | 1 | Probe | |
| Q1_L0_IRQ | 1 | Probe | |
| Q1_L0_PCS_STATUS | 1 | Probe | |
| Q1_L0_PHY_INTERRUPT | 1 | Probe | |
| Instance Q1 Lane 1 | |||
| Q1_L1_BLOCK_LOCK | 1 | Probe | |
| Q1_L1_HI_BER | 1 | Probe | |
| Q1_L1_IRQ | 1 | Probe | |
| Q1_L1_PCS_STATUS | 1 | Probe | |
| Q1_L1_PHY_INTERRUPT | 1 | Probe | |
| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| Instance Q1 Lane 0 | Refer to the MAC Priority Flow Control, MAC Broadcast Filtering & Address Filtering, MAC Statistic Reporting: TX, and MAC Statistic Reporting: RX signal description in Table 1. | ||
| Q1_L0_init_done | 1 | Probe | |
| Q1_L0_cnt_rst_n | 1 | Source | |
| Q1_L0_cnt_tx_frame_transmitted_good | 32 | Probe | |
| Q1_L0_cnt_tx_frame_pause_mac_ctrl | 32 | Probe | |
| Q1_L0_cnt_tx_frame_error_txfifo_overflow | 32 | Probe | |
| Q1_L0_cnt_tx_frame_is_fe | 32 | Probe | |
| Q1_L0_cnt_rx_frame_received_good | 32 | Probe | |
| Q1_L0_rpt_rx_frame_length | 15 | Probe | |
| Q1_L0_cnt_rx_frame_error_fcs | 32 | Probe | |
| Q1_L0_cnt_rx_frame_pause_mac_ctrl | 32 | Probe | |
| Q1_L0_cnt_rx_frame_errors | 32 | Probe | |
| Q1_L0_cnt_rx_frame_received_total | 32 | Probe | |
| Q1_L0_cnt_rx_frame_undersized | 32 | Probe | |
| Q1_L0_cnt_rx_frame_oversized | 32 | Probe | |
| Q1_L0_cnt_rx_frame_mismatched_length | 32 | Probe | |
| Q1_L0_cnt_rx_frame_filtered_by_address | 32 | Probe | |
| Q1_L0_tx_pause_busy | 1 | Probe | |
| Q1_L0_rx_pause_ignore | 1 | Source | |
| Q1_L0_rx_address_filtering_mask | 48 | Source | |
| Q1_L0_tx_pause_gen | 1 | Source | |
| Q1_L0_tx_pause_quant | 16 | Source | |
| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| Instance Q1 Lane 1 | Refer to the MAC Priority Flow Control, MAC Broadcast Filtering & Address Filtering, MAC Statistic Reporting: TX, and MAC Statistic Reporting: RX signal description in Table 1. | ||
| Q1_L1_init_done | 1 | Probe | |
| Q1_L1_cnt_tx_frame_transmitted_good | 32 | Probe | |
| Q1_L1_cnt_tx_frame_pause_mac_ctrl | 32 | Probe | |
| Q1_L1_cnt_tx_frame_error_txfifo_overflow | 32 | Probe | |
| Q1_L1_cnt_tx_frame_is_fe | 32 | Probe | |
| Q1_L1_cnt_rx_frame_received_good | 32 | Probe | |
| Q1_L1_rpt_rx_frame_length | 15 | Probe | |
| Q1_L1_cnt_rx_frame_error_fcs | 32 | Probe | |
| Q1_L1_cnt_rx_frame_pause_mac_ctrl | 32 | Probe | |
| Q1_L1_cnt_rx_frame_errors | 32 | Probe | |
| Q1_L1_cnt_rx_frame_received_total | 32 | Probe | |
| Q1_L1_cnt_rx_frame_undersized | 32 | Probe | |
| Q1_L1_cnt_rx_frame_oversized | 32 | Probe | |
| Q1_L1_cnt_rx_frame_mismatched_length | 32 | Probe | |
| Q1_L1_cnt_rx_frame_filtered_by_address | 32 | Probe | |
| Q1_L1_tx_pause_busy | 1 | Probe | |
| Q1_L1_cnt_rst_n | 1 | Source | |
| Q1_L1_rx_pause_ignore | 1 | Source | |
| Q1_L1_rx_address_filtering_mask | 48 | Source | |
| Q1_L1_tx_pause_gen | 1 | Source | |
| Q1_L1_tx_pause_quant | 16 | Source | |
| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| Q1_apb_rom_end_w | 1 | Probe | The assertion of this signal indicates that all the configuration settings stored in the built-in APB ROM are executed. |
| Q1_usr_apb_start_w | 1 | Source | This signal enables you to manually trigger APB
requests. Pre-requisite: Before asserting this signal, you need
to ensure that signal q1_apb_rom_end is asserted,
indicating that the APB master is available to grant the APB
commands from this signal.Efinix
recommends that you control this signal column by selecting
Active-High from a drop-down list in the
control column. This signal operates on its rising edge;
i.e., its assertion triggers 1 APB request. Prior to the assertion
of this signal, APB signals ( usr_apb_write,
usr_apb_addr, and
usr_apb_pwdata) need to be assigned and
stable.To trigger another APB request, this signal needs
to return to 0 first, then re-assert to trigger the
subsequent APB request. |
| Q1_usr_apb_write_w | 1 | Source | APB write. |
| Q1_usr_apb_addr_w | 24 | Source | APB address. |
| Q1_usr_apb_pwdata_w | 32 | Source | APB write data. |
| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| Q1_ram_usr_wren_w | 1 | Source | Drive this signal to permanent 0 to retrieve the APB
PRDATA with the corresponding APB_PADDRESS from the built-in APB
RAM. |
| Q1_ram_usr_addr_w | 5 | Source | Every APB read operation stores the APB PRDATA and the
APB_PADDRESS into the built-in APB RAM in ascending order. If you
set the ram_usr_addr to ‘h00, the
ram_dout_d and ram_dout_a
respectively display the APB PRDATA and APB_PADDRESS of the
1st APB read command. Setting
ram_usr_addr to ‘h01 displays
the results of the 2nd APB read command, and so
on. |
| Q1_ram_dout_d_w | 32 | Probe | |
| Q1_ram_dout_a_w | 24 | Probe |
| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| Overall Status of Checkers | Consolidated status of all relevant checkers. The passing criteria of checkers may vary, depending on the macro enablement. The assertion of this signal indicates that all the passing criteria are met. | ||
| PASS_STATUS | 1 | Probe | |
| Checker: RX TUSER | The assertion of this signal indicates that there is no
error in the RX data path. If this signal is 0, it
indicates errors in the RX PCS and/or the Ethernet 10G MAC
core. |
||
| Q1_L0_rx_tuser_pass | 1 | Probe | |
| Q1_L1_rx_tuser_pass | 1 | Probe | |
| Checker: Error Frame at TX | The assertion of this signal indicates that there is no error frame in the RX data path. | ||
| Q1_L0_fe_pkt_pass | 1 | Probe | |
| Q1_L1_fe_pkt_pass | 1 | Probe | |
| Checker: KR Training Status | The assertion of this signal indicates that the 10G-KR link training is successful. | ||
| Q1_L0_kr_training_pass | 1 | Probe | |
| Q1_L1_kr_training_pass | 1 | Probe | |
| Checker: PCS Fault Status | The assertion of this signal indicates that both the TX
and RX paths in the 10G PCS are fault-free. Refer to the status
register description in the Status Register table
in the Register Map chapter of the Titanium Ethernet 10GBase-KR User Guide. |
||
| Q1_L0_pcs_fault_pass | 1 | Probe | |
| Q1_L1_pcs_fault_pass | 1 | Probe | |
| Checker: Phy Interrupt | The assertion of this signal indicates that during the PHY power-up handshake, the PHY power state transitions are as expected. | ||
| Q1_L0_phy_interrupt_pass | 1 | Probe | |
| Q1_L1_phy_interrupt_pass | 1 | Probe | |
| Checker: Auto Negotiation | The assertion of this signal indicates that the 10G PCS
has achieved successful auto negotiation with the link partner. Refer to
the auto negotiation link partner register description in the
usxgmii_an_lp_register table in the Register
Map chapter of the Titanium Ethernet 10GBase-KR User Guide. |
||
| Q1_L0_auto_nego_pass | 1 | Probe | |
| Q1_L1_auto_nego_pass | 1 | Probe | |