Signal_ok

After the assertion of phy_init_done, you must create an APB driver to configure signal_ok, based on the register mapping in the Register Map chapter (refer to control_register table, status_register table, and interrupt_status_register table) of the Titanium Ethernet 10GBase-KR User Guide. The APB interface is a common interface shared across all 4 lanes within a quad. The signal_ok enables the RX path in the FPGA Ethernet 10G PCS. Figure 1 includes an illustration of APB Write to enable PCS RX in Lane 2.

Figure 1. Power Up Handshake with the FPGA Transceiver PHY and PCS

Any deassertion of phy_init_done signals that the current CDR-locked-to-data condition has lost lock. When this occurs, you must set the signal_ok to 0 to disable the RX path in the FPGA Ethernet 10G PCS. Upon the recovery of phy_init_done, you must reconfigure the signal_ok to 1 to re-enable the RX path in the FPGA Ethernet 10G PCS.

When the PMA_CMN_READY signal deasserts, it indicates that the FPGA transceiver PHY is no longer functional. If this occurs, all the per-lane reset input signals (i.e., init_rst_n,


                mac_reset_n

, and cnt_rst_n) must be asserted. You must set the signal_ok to 0 to disable the RX path in the FPGA Ethernet 10G PCS. Once the FPGA PHY recovers from reset, you must repeat the entire power-up handshake by deasserting the init_rst_n to start over the power-up sequence.

Note: The APB interface is unaffected by phy_init_done, PMA_CMN_READY, PCS_RST_N_TX, or PCS_RST_N_TX (both the latter signals are from FPGA Ethernet 10G PCS).