Efinix, Inc.
  • Introduction
    • Features
    • Device Support
    • Resource Utilization
    • Release Notes
  • Functional Description
    • Block Diagram
    • Clock Sources
    • Reset Signals
    • Power Up Handshake with FPGA Transceiver
      • CDR-Locked-to-Data
      • Signal_ok
    • Ethernet Packets, Frames, and IPG
    • User Interface AXI ST 64
      • TX AXI ST 64
      • RX AXI ST 64
    • CRC Generation and Check
    • Programmable Inter Packet Gap (IPG)
    • XGMII Interface
      • XGMII TX
      • XGMII RX
    • Data Streaming Mode for Transmission
      • Cut Through Mode
      • Store Forward Mode
    • Automatic Padding for Short TX Frames
    • Terminating Bad TX Frames
      • Non-Compliant TX_AXI_TLAST
      • Assertion of TX_AXI_TUSER
      • Non-Streaming TX Data
      • Dropped TX_AXI_TVALID Before End of Frame
      • TX FIFO Overflow
    • Erroneous RX Frame
      • Undersized RX Frame
      • Oversized RX Frame
      • Mismatched Length RX Frame
      • Frame Check Sequence (FCS) Error
      • Non-Streaming RX Data Frame
      • Error Frame
    • Address Filtering and Broadcast Filtering at RX
    • Priority Flow Control (Duplex Mode)
      • Send Pause Frame at TX
      • Decoding Pause Frame at RX
    • Link Fault Sequence
    • Statistic Reporting
      • cnt_tx_frame_transmitted_good
      • cnt_tx_frame_pause_mac_ctrl
      • cnt_tx_frame_is_fe
      • cnt_tx_frame_error_txfifo_overflow
      • rpt_rx_frame_length
      • cnt_rx_frame_undersized
      • cnt_rx_frame_oversized
      • cnt_rx_frame_mismatched_length
      • cnt_rx_frame_error_fcs
      • cnt_rx_frame_filtered_by_address
      • cnt_rx_frame_pause_mac_ctrl
      • cnt_rx_frame_errors
      • cnt_rx_frame_received_good
      • cnt_rx_frame_received_total
  • Latency
  • Efinity: IP Catalog, Interface Designer, and Integration
    • IP Catalog
    • Interface Designer
    • Top Level Module
    • IP Manager
  • Customizing the Ethernet 10G MAC
  • Ports
  • Ethernet 10G MAC Example Design
    • Example Design Macros
    • Enabling the Macros in the Example Design
    • Generating the Example Design
    • Virtual I/O Debugger Settings
  • Ethernet 10G MAC Testbench
  • Acronyms and Abbreviations

Interface Designer

Refer to Chapter 16 10Gbase-KR Interface of Titanium Interfaces User Guide.

Parent topic: Efinity: IP Catalog, Interface Designer, and Integration

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