Decoding Pause Frame at RX

At RX, the Ethernet 10G MAC core decodes and identifies the pause frame from the RX Ethernet frames which are coming from the Ethernet 10G PCS. The RX pause frame is decoded based on the reserved address 01-80-C2-00-00-01. Once the RX pause frame is identified, it is decoded to extract the embedded RX_QUANT. Once decoded, the RX_QUANT value is directed to the TX channels, where the pause mechanism is enabled with the RX_QUANT value.

A quanta is the time required to transmit 512 bits of data at port speed. For Ethernet 10G MAC core, RX_QUANT = 1 signifies that the XGMII TX pauses for 64 octets. When the pause mechanism takes place, the XGMII TX outputs IDLE for the duration of RX_QUANT. The duration of RX_QUANT starts the pause count at Octet0.

You may set the rx_ignore port to ignore the decoded RX_QUANT, and the pause mechanism is disabled. The rx_ignore port must be assigned with pseudo-static input.

Note: The RX pause frame is not subject to address filtering. The RX pause frame is decoded purely based on the pause frame unique address, frame type ID, pause opcode, and CRC octets.

The RX pause frame is valid if it passes a CRC check. If the RX pause frame contains a CRC Error, then the RX pause frame is erroneous. The extracted RX_QUANT is invalid and is not propagated to the TX channel. At the same time, like the normal RX frames, the RX pause frame is converted from the XGMII interface and outputs at the RX AXI ST interface. Refer to Figure 1 for more details.

Note: RX pause frame, whether undersized or oversized, is processed as a valid RX pause frame.

Upon arriving at the TX channel, the decoded RX_QUANT has higher priority over PAUSE_REQUEST (triggered by tx_pause_gen) and TX AXI ST data frame transfers. However, if the decoded RX_QUANT arrives while a TX pause frame or TX data frame is being transferred, the pause mechanism is queued and applied only after the ongoing TX activity completes.

Figure 1 describes the priority flow control among the 3 events. In this illustration, both the IPG and IDLE are interchangeable, and carry the value 07. An IDLE is used to illustrate the XGMII TX output when RX_QUANT is effective, while the IPG is used to illustrate the mandatory insertion of gaps based on the user-configured Programmable Inter Packet Gap between the TX Ethernet frames.

Note:

The Ethernet 10G MAC core is only able to process one RX_QUANT at a time. When RX_QUANT is active and effective at the TX channel, and there is a new incoming RX pause frame, the new RX_QUANT is ignored and blocked from disrupting the ongoing (or queued) pause mechanism.
In Efinity v2025.2.288.4.xxx and later, any valid incoming (and passing the CRC check) RX pause frame overwrites the ongoing (or queued) RX_QUANT. Figure 2 depicts how Ethernet 10G MAC core processes multiple RX pause frames.
In Efinity v2025.2.288.4.xxx and later, RX pause frame with RX_QUANT = 0 overwrites the existing RX_QUANT to 0, effectively terminating the existing RX pause mechanism. See Figure 3.

Figure 1. Priority Flow Control at XGMII TX