CDR-Locked-to-Data

To achieve the CDR-locked-to-data stage, the RX path of the FPGA transceiver PHY must receive continuous toggling signals from its Link Partner. Hence, upon the assertion of PMA_CMN_READY, you must ensure that the Link Partner sends continuous toggling signals to the RX path of the FPGA transceiver PHY.

During the power-up, the FPGA Ethernet 10G PCS's PCS_RST_N_TX must deassert to allow the TX path to continuously send IDLE packets to the Link Partner’s RX path.

If the FPGA Ethernet 10G PCS’s PCS_RST_N_TX and PCS_RST_N_RX, and the Ethernet 10G MAC core’s mac_reset_n signals are independently driven, once the PMA_CMN_READY is asserted, you must deassert the FPGA Ethernet 10G PCS’s PCS_RST_N_TX to 1. At the RX path, upon the assertion of phy_init_done, you can deassert both the FPGA Ethernet 10G PCS’s PCS_RST_N_RX and Ethernet 10G MAC core’s mac_reset_n to 1.

If the FPGA Ethernet 10G PCS’s PCS_RST_N_TX and PCS_RST_N_RX, and the Ethernet 10G MAC core’s mac_reset_n signals are driven from the same source, all the 3 reset signals must deassert to 1 upon the assertion of PMA_CMN_READY.