Generating the Example Design

Use the following steps to generate the example design from the IP Catalog.
  1. Create a new project.
  2. Select the Ethernet 10G MAC core from the IP Catalog and set your configurations.
  3. In the Deliverables tab, turn on the Example Design (efx_ethernet_10g_exp).
  4. Click Generate.

The example design is available in <project path>\ip\<ip-module-name>\efx_ethernet_10g_exp directory.

To migrate the example design into the Functional Verification Testbench:
  1. Close the existing project.
  2. To open the example design, select <project path>\ip\<ip-module-name>\ efx_ethernet_10g_exp\efx_ethernet_10g_exp.xml
  3. Enable the VERIF macro. This step is mandatory.
    Note: You may enable or disable any macro combination of the KR_ENABLE, AN_ENABLE, or LOOPBACK.
  4. Compile the design.
  5. In the Functional Verification Testbench, instantiate and connect the example design based on the Table 1.
  6. Connect to drive input vectors from the Functional Verification Testbench into the Ethernet 10G MAC core.
  7. If you enable the LOOPBACK macro, you need to tie off all inputs of the APB modules.
The PHY power-up sequence interface is still connected to the FPGA PHY. Hence, in user mode, the power-up sequence handshake takes place, and the forwarded clock is ON to clock the Ethernet 10G MAC core.
Note: The LOOPBACK macro is only applicable to Q1_L0 in the example design.
To load the example design into the FPGA development board:
  1. Close the existing project.
  2. To open the example design, select <project path>\ip\<ip-module-name>\ efx_ethernet_10g_exp\efx_ethernet_10g_exp.xml
  3. Disable the VERIF macro. This step is mandatory.
    Note: You may enable any macro combination of KR_ENABLE, AN_ENABLE, or LOOPBACK.
  4. Compile the design.
  5. Download the design to your Titanium Ti375 N1156 Development Board.

Table 1. Example Design for Functional Verification Testbench
Signal Name Direction Width Description
Common Clocks and Signals
INIT_CLK Input 1 Connect from the PLL_TR1 in FPGA peripheral.
Q1_APB_CLK Input 1
PLL_LOCKED Input 1
IN_USER Input 1 Connect from the FPGA peripheral.
Instance Q1 Lane 0: Per Lane Clock and Reset
Q1_L0_10gbe_clk Input 1 Connect with the FPGA transceiver’s Q1 lane 0 interface.
Q1_L0_PCS_RST_N_RX Output 1
Q1_L0_PCS_RST_N_TX Output 1
Instance Q1 Lane 0: PCS Interface
Q1_L0_BLOCK_LOCK Input 1 Connect with the FPGA transceiver’s Q1 lane 0 interface.
Q1_L0_PCS_STATUS Input 1
Q1_L0_IRQ Input 1
Q1_L0_HI_BER Input 1
Q1_L0_PHY_INTERRUPT Input 1
Q1_L0_PMA_TX_ELEC_IDLE Output 1
Q1_L0_ETH_EEE_ALERT_EN Output 1
Instance Q1 Lane 0: KR Training Interface
Q1_L0_KR_TRAINING_ENABLE Output 1 Connect with the FPGA transceiver’s Q1 lane 0 interface.
Q1_L0_KR_RESTART_TRAINING Output 1
Q1_L0_KR_TRAINING Input 1
Q1_L0_KR_FRAME_LOCK Input 1
Q1_L0_KR_LOCAL_RX_TRAINED Input 1
Q1_L0_KR_SIGNAL_DETECT Input 1
Q1_L0_KR_TRAINING_FAILURE Input 1
Q1_L0_restart_kr_training_IN Input 1 Connect from the drivers in the Functional Verification Testbench.
Instance Q1 Lane 0: PHY Power Up Sequence Interface
Q1_PMA_CMN_READY1 Input 1 Connect with the FPGA transceiver’s Q1 lane 0 interface.
Q1_L0_PMA_XCVR_PLLCLK_EN Output 1
Q1_L0_PMA_XCVR_PLLCLK_EN_ACK Input 1
Q1_L0_PMA_XCVR_POWER_STATE_REQ Output 4
Q1_L0_PMA_XCVR_POWER_STATE_ACK Input 4
Q1_L0_PMA_RX_SIGNAL_DETECT Input 1
Instance Q1 Lane 0: XGMII Interface
Q1_L0_TXD Output 64 Connect with the FPGA transceiver’s Q1 lane 0 interface.
Q1_L0_TXC Output 8
Q1_L0_RXD Input 64
Q1_L0_RXC Input 8
Instance Q1 Lane 0: Input to Ethernet 10G MAC Core
in_Q1_L0_cnt_rst_n Input 1 Connect from the drivers in the Functional Verification Testbench.
in_Q1_L0_rx_pause_ignore Input 1
in_Q1_L0_rx_address_filtering_mask Input 48
in_Q1_L0_tx_pause_gen Input 1
in_Q1_L0_tx_pause_quant Input 16
Instance Q1: APB Interface
Q1_USER_APB_PSEL Output 1 Connect with the FPGA transceiver’s Q1 interface.
Q1_USER_APB_PWRITE Output 1
Q1_USER_APB_PENABLE Output 1
Q1_USER_APB_PADDR Output 24
Q1_USER_APB_PWDATA Output 32
Q1_USER_APB_PRDATA Input 32
Q1_USER_APB_PREADY Input 1
Q1_USER_APB_PSLVERR Input 1
Instance Q1: APB Modules
in_Q1_ram_usr_wren_w Input 1 Connect from the drivers in the Functional Verification Testbench, applicable only to debug the APB modules in the example design.
For functional use case, initialize each signal to 0.
in_Q1_ram_usr_addr_w Input 6
in_Q1_usr_apb_start_w Input 1
in_Q1_usr_apb_addr_w Input 24
in_Q1_usr_apb_write_w Input 1
in_Q1_usr_apb_pwdata_w Input 32
Instance Q1 Lane 1: Per Lane Clock and Reset
Q1_L1_10gbe_clk Input 1 Connect with the FPGA transceiver’s Q1 lane 1 interface.
Q1_L1_PCS_RST_N_RX Output 1
Q1_L1_PCS_RST_N_TX Output 1
Instance Q1 Lane 1: PCS Interface
Q1_L1_BLOCK_LOCK Input 1 Connect with the FPGA transceiver’s Q1 lane 1 interface.
Q1_L1_PCS_STATUS Input 1
Q1_L1_IRQ Input 1
Q1_L1_HI_BER Input 1
Q1_L1_PHY_INTERRUPT Input 1
Q1_L1_PMA_TX_ELEC_IDLE Output 1
Q1_L1_ETH_EEE_ALERT_EN Output 1
Instance Q1 Lane 1: KR Training Interface
Q1_L1_KR_TRAINING_ENABLE Output 1 Connect with the FPGA transceiver’s Q1 lane 1 interface.
Q1_L1_KR_RESTART_TRAINING Output 1
Q1_L1_KR_TRAINING Input 1
Q1_L1_KR_FRAME_LOCK Input 1
Q1_L1_KR_LOCAL_RX_TRAINED Input 1
Q1_L1_KR_SIGNAL_DETECT Input 1
Q1_L1_KR_TRAINING_FAILURE Input 1
Q1_L1_restart_kr_training_IN Input 1 Connect from the driver in the Functional Verification Testbench.
Instance Q1 Lane 1: PHY Power Up Sequence Interface
Q1_PMA_CMN_READY1 Input 1 Connect with the FPGA transceiver’s Q1 lane 1 interface.
Q1_L1_PMA_XCVR_PLLCLK_EN Output 1
Q1_L1_PMA_XCVR_PLLCLK_EN_ACK Input 1
Q1_L1_PMA_XCVR_POWER_STATE_REQ Output 4
Q1_L1_PMA_XCVR_POWER_STATE_ACK Input 4
Q1_L1_PMA_RX_SIGNAL_DETECT Input 1
Instance Q1 Lane 1: XGMII Interface
Q1_L1_TXD Output 64 Connect with the FPGA transceiver’s Q1 lane 1 interface.
Q1_L1_TXC Output 8
Q1_L1_RXD Input 64
Q1_L1_RXC Input 8
Instance Q1 Lane 1: Input to Ethernet 10G MAC Core
in_Q1_L1_cnt_rst_n Input 1 Connect from the drivers in the Functional Verification Testbench.
in_Q1_L1_rx_pause_ignore Input 1
in_Q1_L1_rx_address_filtering_mask Input 48
in_Q1_L1_tx_pause_gen Input 1
in_Q1_L1_tx_pause_quant Input 16
JTAG Interface
jtag_vio_CAPTURE Input 1 Connect from the drivers in the Functional Verification Testbench, applicable only when debugging the APB modules in the example design.
For functional use case, initialize each signal to 0 and leave the output port unconnected.
jtag_vio_DRCK Input 1
jtag_vio_RESET Input 1
jtag_vio_RUNTEST Input 1
jtag_vio_SEL Input 1
jtag_vio_SHIFT Input 1
jtag_vio_TCK Input 1
jtag_vio_TDI Input 1
jtag_vio_TMS Input 1
jtag_vio_UPDATE Input 1
jtag_vio_TDO Output 1
Example Design Checker
PASS_STATUS Output 1 Connect to the scoreboard or checker in the Functional Verification Testbench.
Table 2. Example Design Project Files
File Name Description
efx_ethernet_10g_exp.sv Example design of top-level wrapper.
<user_given_ip_name>.sv2 The generated Ethernet 10G MAC file based on user configuration in Efinity IP Manager.
efx_ethernet_10g_exp.sdc Constraint file for example design.
efx_q1_rom_mif.mem APB ROM initialization Hex file for Quad 1.
efx_q1_rom_mif_an.mem APB ROM initialization Hex file for Quad 1. To be used with AN_ENABLE macro.
efx_mac10gbe_exp_apb_master.v2 APB master controller module.
efx_mac10gbe_exp_apb_halt.v2 APB halt controller module.
efx_mac10gbe_exp_pat_gen.v Pattern generator module.
efx_mac10gbe_exp_checker.sv Checker module to validate data received.
efx_resetsync.v Reset the synchronizer module.
efx_asyncreg.v2 Asynchronous register module.
debug_top.v Verilog file for EFX debug module.
debug_profile.json Virtual I/O Debugger core file. Load this file in the Efinity Virtual I/O Debugger to customize the example design. See Virtual I/O Debugger Settings.
1 Q1_PMA_CMN_READY is a common input signal to instances Q1 Lane 0 and Q1 Lane 1.
2 This module is encrypted.