Enabling the Macros in the Example Design

To enable macros for Efinity compilation.
  1. In the active example design, go to File > Edit Project. The Project Editor opens.
  2. Go to the Synthesis tab.
  3. At the Verilog define Macro section, click + to add new macros.
  4. Type in the name of the macro and set Value to 1.
    Note: When enabling the macros, always set the Value to 1. Setting the macro to a different value does not disable the macro.
  5. To disable a macro, you have to remove it from the Verilog define Macro section. To remove a macro, select the desired macro and click -.
Figure 1. Enabling Macro in the Example Design